SBOS079B March   1999  – June 2015 OPA2277 , OPA277 , OPA4277

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for OPA277
    5. 6.5 Thermal Information for OPA2277
    6. 6.6 Thermal Information for OPA4277
    7. 6.7 Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA
    8. 6.8 Electrical Characteristics for OPAx277AIDRM
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Offset Voltage Adjustment
      3. 7.3.3 Input Protection
      4. 7.3.4 Input Bias Current Cancellation
      5. 7.3.5 EMI Rejection Ratio (EMIRR)
        1. 7.3.5.1 EMIRR IN+ Test Configuration
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Second-Order Lowpass Filter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Load Cell Amplifier
      3. 8.2.3 Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction Compensation
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 DFN Package
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 WEBENCH Filter Designer Tool
        2. 11.1.1.2 TINA-TI (Free Software Download)
        3. 11.1.1.3 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
      2. 11.2.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
  • P|8
  • DRM|8
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, Vs = (V+) – (V–) 36 V
Input voltage (V–) –0.7 (V+) +0.7 V
Output short-circuit(2) Continuous
Operating temperature –55 125 °C
Junction temperature 150 °C
Lead temperature 300 °C
Storage temperature, Tstg –55 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage, Vs = (V+) – (V–) 4 (±2) 30 (±15) 36 (±18) V
Specified temperature –40 +85 °C

6.4 Thermal Information for OPA277

THERMAL METRIC(1) OPA277 UNIT
P (PDIP) D (SOIC) DRM (VSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 49.2 110.1 40.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.4 52.2 41.3 °C/W
RθJB Junction-to-board thermal resistance 26.4 52.3 16.7 °C/W
ψJT Junction-to-top characterization parameter 15.4 10.4 0.6 °C/W
ψJB Junction-to-board characterization parameter 26.3 51.5 16.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information for OPA2277

THERMAL METRIC(1) OPA2277 UNIT
P (PDIP) D (SOIC) DRM (VSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 47.2 107.4 39.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 36.0 45.8 36.9 °C/W
RθJB Junction-to-board thermal resistance 24.4 47.9 15.4 °C/W
ψJT Junction-to-top characterization parameter 13.4 5.7 0.4 °C/W
ψJB Junction-to-board characterization parameter 24.3 47.3 15.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Thermal Information for OPA4277

THERMAL METRIC(1) OPA4277 UNIT
D (SOIC) P (PDIP)
14 PINS
RθJA Junction-to-ambient thermal resistance 67.0 66.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.1 20.5 °C/W
RθJB Junction-to-board thermal resistance 22.5 26.8 °C/W
ψJT Junction-to-top characterization parameter 2.2 2.1 °C/W
ψJB Junction-to-board characterization parameter 22.1 26.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.7 Electrical Characteristics for OPAx277P, OPAx277U, and OPAx277xA

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER TEST CONDITIONS OPA277P, U
OPA2277P, U
OPA277PA, UA
OPA2277PA, UA
OPA4277PA, UA
UNIT
MIN TYP(2) MAX MIN TYP (2) MAX
OFFSET VOLTAGE
V0S Input Offset Voltage ±10 ±20 ±20 ±50 µV
Input Offset Voltage Over Temperature OPA277P, U (high-grade, single) TA = –40°C to 85°C ±30 µV
OPA2277P, U (high-grade, dual) ±50
All PA, UA, Versions ±100
AIDRM Versions
dV0S/dT Input Offset Voltage Drift OPA277P, U (high-grade, single) TA = –40°C to 85°C ±0.1 ±0.15 µV/°C
OPA2277P, U (high-grade, dual) ±0.1 ±0.25
All PA, UA, AIDRM Versions ±0.15 ±1
Input Offset Voltage: (all models) vs Time 0.2 See (1) µV/mo
vs Power Supply (PSRR) VS = ±2 V to ±18 V ±0.3 ±0.5 See (1) ±1 µV/V
TA = –40°C to 85°C ±0.5 ±1
Channel Separation (dual, quad) DC 0.1 See (1) µV/V
INPUT BIAS CURRENT
IB Input Bias Current TA = –40°C to 85°C ±0.5 ±1 See (1) ±2.8 nA
±2 ±4
IOS Input Offset Current TA = –40°C to 85°C ±0.5 ±1 See (1) ±2.8 nA
±2 ±4
NOISE
Input Voltage Noise, f = 0.1 to 10 Hz 0.22 See (1) µVPP
en Input Voltage Noise Density f = 10 Hz 12 See (1) nV/√Hz
f = 100 Hz 8 See (1)
f = 1 kHz 8 See (1)
f = 10 kHz 8 See (1)
in Current Noise Density, f = 1 kHz 0.2 See (1) pA/√Hz
INPUT VOLTAGE RANGE
VCM Common-Mode Voltage Range (V–)+2 (V+)–2 See (1) See (1) V
CMRR Common-Mode Rejection VCM = (V–) +2 V to (V+) –2 V 130 140 115 See (1) dB
TA = –40°C to 85°C 128 115
INPUT IMPEDANCE
Differential 100 || 3 See (1) MΩ || pF
Common-Mode VCM = (V–) +2 V to (V+) –2 V 250 || 3 See (1) GΩ || pF
OPEN-LOOP GAIN
AOL Open-Loop Voltage Gain VO = (V–)+0.5 V to
(V+)–1.2 V,
RL = 10 kΩ
140 See (1) dB
VO = (V–)+1.5 V to
(V+)–1.5 V,
RL = 2 kΩ
126 134 See (1) See (1)
VO = (V–)+1.5 V to
(V+)–1.5 V,
RL = 2 kΩ
126 See (1) dB
TA = –40°C to 85°C
FREQUENCY RESPONSE
GBW Gain-Bandwidth Product 1 See (1) MHz
SR Slew Rate 0.8 See (1) V/µs
Settling Time 0.1% VS = ±15 V,
G = 1,
10-V Step
14 See (1) µs
0.01% 16 See (1)
Overload Recovery Time VIN × G = VS 3 See (1) µs
THD+N Total Harmonic Distortion + Noise 1 kHz, G = 1,
VO = 3.5 Vrms
0.002% See (1)
OUTPUT
VO Voltage Output RL = 10 kΩ (V–)+0.5 (V+)–1.2 See (1) See (1) V
TA = –40°C to +85°C (V–)+0.5 (V+)–1.2 See (1) See (1)
RL = 2 kΩ (V–)+1.5 (V+)–1.5 See (1) See (1)
TA = –40°C to +85°C (V–)+1.5 (V+)–1.5 See (1) See (1)
ISC Short-Circuit Current ±35 See (1) mA
CLOAD Capacitive Load Drive See (3)
ZO Open-loop output impedance f = 1 MHz 40 See (1) Ω
POWER SUPPLY
VS Specified Voltage Range ±5 ±15 See (1) See (1) V
Operating Voltage Range ±2 ±18 See (1) See (1) V
IQ Quiescent Current (per amplifier) IO = 0 ±790 ±825 See (1) See (1) µA
TA = –40°C to 85°C ±900 See (1)
TEMPERATURE RANGE
Specified Range –40 85 See (1) See (1) °C
Operating Range –55 125 See (1) See (1) °C
(1) Specifications are the same as OPA277P, U.
(2) VS = ±15 V

6.8 Electrical Characteristics for OPAx277AIDRM

At TA = 25°C, and RL = 2 kΩ, unless otherwise noted
PARAMETER TEST CONDITIONS OPA277AIDRM
OPA2277AIDRM
UNIT
MIN TYP(2) MAX
OFFSET VOLTAGE
V0S Input Offset Voltage ±35 ±100 µV
Input Offset Voltage Over Temperature OPA277P, U (high-grade, single) TA = –40°C to 85°C µV
OPA2277P, U (high-grade, dual)
All PA, UA, Versions
AIDRM Versions ±165
dV0S/dT Input Offset Voltage Drift OPA277P, U (high-grade, single) TA = –40°C to 85°C µV/°C
OPA2277P, U (high-grade, dual)
All PA, UA, AIDRM Versions ±0.15 ±1
Input Offset Voltage: (all models) vs Time See (1) µV/mo
vs Power Supply (PSRR) VS = ±2 V to ±18 V See (1) ±1 µV/V
TA = –40°C to 85°C ±1
Channel Separation (dual, quad) DC See (1) µV/V
INPUT BIAS CURRENT
IB Input Bias Current TA = –40°C to 85°C ±2.8 nA
±4
IOS Input Offset Current TA = –40°C to 85°C ±2.8 nA
±4
NOISE
Input Voltage Noise, f = 0.1 to 10 Hz See (1) µVPP
en Input Voltage Noise Density f = 10 Hz See (1) nV/√Hz
f = 100 Hz See (1)
f = 1 kHz See (1)
f = 10 kHz See (1)
in Current Noise Density, f = 1 kHz See (1) pA/√Hz
INPUT VOLTAGE RANGE
VCM Common-Mode Voltage Range See (1) See (1) V
CMRR Common-Mode Rejection VCM = (V–) +2 V to (V+) –2 V 115 See (1) dB
TA = –40°C to 85°C 115
INPUT IMPEDANCE
Differential See (1) MΩ || pF
Common-Mode VCM = (V–) +2 V to (V+) –2 V See (1) GΩ || pF
OPEN-LOOP GAIN
AOL Open-Loop Voltage Gain VO = (V–)+0.5 V to
(V+)–1.2 V,
RL = 10 kΩ
See (1) dB
VO = (V–)+1.5 V to
(V+)–1.5 V,
RL = 2 kΩ
See (1) See (1)
VO = (V–)+1.5 V to
(V+)–1.5 V,
RL = 2 kΩ
See (1) dB
TA = –40°C to 85°C
FREQUENCY RESPONSE
GBW Gain-Bandwidth Product See (1) MHz
SR Slew Rate See (1) V/µs
Settling Time 0.1% VS = ±15 V,
G = 1,
10-V Step
See (1) µs
0.01% See (1)
Overload Recovery Time VIN × G = VS See (1) µs
THD+N Total Harmonic Distortion + Noise 1 kHz, G = 1,
VO = 3.5 Vrms
See (1)
OUTPUT
VO Voltage Output RL = 10 kΩ See (1) See (1) V
TA = –40°C to +85°C See (1) See (1)
RL = 2 kΩ See (1) See (1)
TA = –40°C to +85°C See (1) See (1)
ISC Short-Circuit Current See (1) mA
CLOAD Capacitive Load Drive
ZO Open-loop output impedance f = 1 MHz See (1) Ω
POWER SUPPLY
VS Specified Voltage Range See (1) See (1) V
Operating Voltage Range See (1) See (1) V
IQ Quiescent Current (per amplifier) IO = 0 See (1) See (1) µA
TA = –40°C to 85°C See (1)
TEMPERATURE RANGE
Specified Range See (1) See (1) °C
Operating Range See (1) See (1) °C
(1) Specifications are the same as OPA277P, U.
(2) VS = ±15 V

6.9 Typical Characteristics

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
OPA277 OPA2277 OPA4277 sbos079_typchar_1.gif
Figure 1. Open-Loop Gain and Phase vs Frequency
OPA277 OPA2277 OPA4277 tc_input_current_noise_spec_density_bos079.gif
Figure 3. Input Noise and Current Noise Spectral Density
vs Frequency
OPA277 OPA2277 OPA4277 sbos079_typchar_5.gif
Figure 5. Channel Separation vs Frequency
OPA277 OPA2277 OPA4277 sbos079_typchar_7.gif
Figure 7. Offset Voltage Production Distribution
OPA277 OPA2277 OPA4277 sbos079_typchar_9.gif
Figure 9. Warm-Up Offset Voltage Drift
OPA277 OPA2277 OPA4277 sbos079_typchar_11.gif
Figure 11. Input Bias Current vs Temperature
OPA277 OPA2277 OPA4277 sbos079_typchar_13.gif
Figure 13. Change in Input Bias Current vs
Power Supply Voltage
OPA277 OPA2277 OPA4277 sbos079_typchar_15.gif
Figure 15. Quiescent Current vs Supply Voltage
OPA277 OPA2277 OPA4277 sbos079_typchar_17.gif
Figure 17. Maximum Output Voltage vs Frequency
OPA277 OPA2277 OPA4277 sbos079_typchar_19.gif
Figure 19. Small-Signal Overshoot vs Load Capacitance
OPA277 OPA2277 OPA4277 sbos079_typchar_21.gif
Figure 21. Small-Signal Step Response
G= +1, CL = 0, VS = ±15 V
OPA277 OPA2277 OPA4277 D002_sbos079.gif
Figure 23. Open-Loop Output Impedance
VS = ±15 V
OPA277 OPA2277 OPA4277 sbos079_typchar_2.gif
Figure 2. Power Supply and Common-Mode Rejection vs Frequency
OPA277 OPA2277 OPA4277 sbos079_typchar_4.gif
Figure 4. Input Noise Voltage vs Time
OPA277 OPA2277 OPA4277 sbos079_typchar_6.gif
Figure 6. Total Harmonic Distortion + Noise vs Frequency
OPA277 OPA2277 OPA4277 sbos079_typchar_8.gif
Figure 8. Offset Voltage Drift Production Distribution
OPA277 OPA2277 OPA4277 sbos079_typchar_10.gif
Figure 10. AOL, CMR, PSR vs Temperature
OPA277 OPA2277 OPA4277 sbos079_typchar_12.gif
Figure 12. Quiescent Current and Short-Circuit Current vs Temperature
OPA277 OPA2277 OPA4277 sbos079_typchar_14.gif
Figure 14. Change in Input Bias Current vs
Common-Mode Voltage
OPA277 OPA2277 OPA4277 sbos079_typchar_16.gif
Figure 16. Settling Time vs Closed-Loop Gain
OPA277 OPA2277 OPA4277 sbos079_typchar_18.gif
Figure 18. Output Voltage Swing vs Output Current
OPA277 OPA2277 OPA4277 sbos079_typchar_20.gif
Figure 20. Large-Signal Step Response
G = 1, CL = 1500 pF, VS = ±15 V
OPA277 OPA2277 OPA4277 sbos079_typchar_22.gif
Figure 22. Small-Signal Step Response
G= 1, CL = 1500 pF, VS = ±15 V