At VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted).
| Simulated with no output
load |
Figure 7-42 Open-Loop Gain and Phase vs Frequency
Figure 7-44 Large-Signal Response vs Supply Voltage
Figure 7-46 Harmonic Distortion vs Frequency vs Supply Voltage
| Measured then fit to ideal
1/f model |
Figure 7-48 Auxiliary Input Stage Voltage Noise Density vs Frequency
Figure 7-50 Common-Mode Rejection Ratio vs Frequency
| Simulated curves,
VS = 24 V |
Figure 7-52 Power
Supply Rejection Ratio vs Frequency
| Abs (VIN,Diff
(max)) = VS when VS <
7 V |
Figure 7-54 Input
Bias Current vs Differential Input Voltage
Figure 7-56 Input
Offset Voltage vs Ambient Temperature
| 27000 units, µ = 16 µV, σ = 63 µV, VS = 24
V |
Figure 7-58 Input
Offset Voltage Distribution
Figure 7-43 Large-Signal Response vs Supply Voltage
Figure 7-45 Harmonic Distortion vs Frequency vs Supply Voltage
| Measured then fit to ideal
1/f model |
Figure 7-47 Input
Voltage Noise Density vs Frequency
Figure 7-49 Open-Loop Output Impedance vs Frequency
Figure 7-51 Power
Supply Rejection Ratio vs Frequency
Figure 7-53 Input
Bias Current vs Input Common-Mode Voltage
| 32 units, SOIC package,
VS = ±5 V |
Figure 7-55 Quiescent Current vs Ambient Temperature
| 27000 units, µ = 3.82 mA, σ = 17 µA, VS = 24
V |
Figure 7-57 Quiescent Current Distribution
| –40°C to +125°C fit, 32
units, µ = –0.15 µV/°C, σ = 2.5 µV/°C |
Figure 7-59 Input
Offset Voltage Drift Distribution