JAJSHS6D August   2019  – July 2020 OPA810

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: 10 V
    6. 7.6  Electrical Characteristics: 24 V
    7. 7.7  Electrical Characteristics: 5 V
    8. 7.8  Typical Characteristics: VS = 10 V
    9. 7.9  Typical Characteristics: VS = 24 V
    10. 7.10 Typical Characteristics: VS = 5 V
    11. 7.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 OPA810 Architecture
      2. 8.3.2 ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±2.375 V to ±13.5 V)
      2. 8.4.2 Single-Supply Operation (4.75 V to 27 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Amplifier Gain Configurations
      2. 9.1.2 Selection of Feedback Resistors
      3. 9.1.3 Noise Analysis and the Effect of Resistor Elements on Total Noise
    2. 9.2 Typical Applications
      1. 9.2.1 Transimpedance Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 High-Z Input Data Acquisition Front-End
      3. 9.2.3 Multichannel Sensor Interface
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics: 10 V

Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = mid-supply, RL = 1 kΩ connected to mid-supply(5).
PARAMETERTEST CONDITIONSMINTYPMAXUNITTEST LEVEL(3)
AC PERFORMANCE
SSBWSmall-signal bandwidthG = 1, VO = 20 mVPP, RF = 0 Ω135MHzC
G = 1, VO = 20 mVPP, RF = 0 Ω,
CL = 10 pF		140C
G = –1, VO = 20 mVPP68C
LSBWLarge-signal bandwidthG = 2, VO = 2 VPP41MHzC
GBWPGain-bandwidth product70MHzC
Bandwdith for 0.1-dB flatnessG = 2, VO = 20 mVPP16MHzC
SRSlew rate (20%-80%)(4)G = 2, VO = –2-V to 2-V step200V/µsC
Rise timeVO = 200-mV step4nsC
Fall timeVO = 200-mV step4nsC
Settling time to 0.1%G = 2, VO = 2-V step47nsC
G = 2, VO = 8-V step65C
Settling time to 0.001%G = 2, VO = 2-V step330nsC
G = 2, VO = 8-V step230C
Input overdrive recoveryG = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+ + 0.5 V) input 55nsC
Output overdrive recoveryG = –1, (VS– – 0.5 V) to (VS+ + 0.5 V) input 55nsC
HD2Second-order harmonic distortionf = 100 kHz, RL = 1 kΩ, VO = 2 VPP–120dBcC
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP–101C
HD3Third-order harmonic distortionf = 100 kHz, RL = 1 kΩ, VO = 2 VPP–137dBcC
f = 1 MHz, RL = 1 kΩ, VO = 2 VPP–101C
enInput-referred voltage noiseFlatband, 1/f corner at 1.5 kHz 6.3nV/√ HzC
inInput-referred current noisef = 10 kHz5fA/√ HzC
zOClosed-loop output impedancef = 100 kHz0.007ΩC
DC PERFORMANCE
AOLOpen-loop voltage gainf = DC, VO = ±2.5 V108120dBA
VOSInput offset voltageSOIC package100500µVA
DBV and DCK packages 100715
Input offset voltage driftTA = –40°C to +125°C2.510µV/°CB
Input bias current220pAA
Input offset current120pAA
CMRRCommon-mode rejection ratiof = DC, VCM = –3 V to 1 V, SOIC package80100dBA
TA = –40°C to +125°C, SOIC package80B
INPUT
Allowable input differential voltageSee Figure 7-54±7VC
Common-mode input impedanceIn closed-loop configuration12 || 2GΩ||pFC
Differential input capacitanceIn open-loop configuration0.5pFC
Most positive input voltageΔVOS < 5 mV(1)VS+ + 0.2VS+ + 0.3VA
Most negative input voltageΔVOS < 5 mV(1)VS– – 0.2VS– – 0.3VA
Most positive input voltage for main-JFET stage See Figure 7-17VS+ – 2.9VS+ – 2.5VC
OUTPUT
VOCRHOutput voltage range high RL = 667 ΩVS+ – 0.18VS+ – 0.11VA
VOCRHOutput voltage range highTA = –40°C to +125°C, RL = 667 ΩVS+ – 0.2VB
VOCRLOutput voltage range low RL = 667 ΩVS– + 0.08VS– + 0.15VA
VOCRLOutput voltage range lowTA = –40°C to +125°C, RL = 667 ΩVS– + 0.2VB
IO(max)Linear output drive (sourcing and sinking) VO = 2.65 V, RL = 51 Ω, ΔVOS < 1 mV5275mAA
ISCOutput short-circuit current100mAB
CLCapacitive load drive< 3-dB peaking, RS = 0 Ω10pFC
POWER SUPPLY
IQQuiescent current per channel3.74.6mAA
PSRRPower-supply rejection ratioΔVS = ±2 V(2), SOIC package79100dBA
TA = –40°C to +125°C, SOIC package79B
AUXILIARY CMOS INPUT STAGE
Gain-bandwidth product27MHzC
Input-referred voltage noise f = 1 MHz20nV/√ HzC
Input offset voltageVCM = VS+ – 1.5 V, no load, SOIC Package1.6mVA
Input bias currentVCM = VS+ – 1.5 V220pAA
(1) Change in input offset from its value when input is biased to midsupply.
(2) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +PSRR and –PSRR.
(3) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.
(4) Lower of the measured positive and negative slew rate.
(5) For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted).