JAJSH62O October   2004  – September 2023 PCA9306

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics AC Performance (Translating Down) (EN = 3.3 V)
    7. 6.7  Switching Characteristics AC Performance (Translating Down) (EN = 2.5 V)
    8. 6.8  Switching Characteristics AC Performance (Translating Up) (EN = 3.3 V)
    9. 6.9  Switching Characteristics AC Performance (Translating Up) (EN = 2.5 V)
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Definition of threshold voltage
      2. 8.1.2 Correct Device Set Up
      3. 8.1.3 Disconnecting an I2C target from the Main I2C Bus Using the EN Pin
      4. 8.1.4 Supporting Remote Board Insertion to Backplane with PCA9306
      5. 8.1.5 Switch Configuration
      6. 8.1.6 Controller on Side 1 or Side 2 of Device
      7. 8.1.7 LDO and PCA9306 Concerns
      8. 8.1.8 Current Limiting Resistance on VREF2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable (EN) Pin
      2. 8.3.2 Voltage Translation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Applications of I2C
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bidirectional Voltage Translation
        2. 9.2.2.2 Sizing Pullup Resistors
        3. 9.2.2.3 PCA9306 Bandwidth
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.2.2.3 PCA9306 Bandwidth

The maximum frequency of the PCA9306 device depends on the application. The device can operate at speeds of > 100 MHz given the correct conditions. The maximum frequency is dependent upon the loading of the application.

Figure 6-3 shows a bandwidth measurement of the PCA9306 device using a two-port network analyzer.

However, this is an analog type of measurement. For digital applications, the signal should not degrade up to the fifth harmonic of the digital signal. As a rule of thumb, the frequency bandwidth should be at least five times the maximum digital clock rate. This component of the signal is very important in determining the overall shape of the digital signal. In the case of the PCA9306 device, digital clock frequency of >100 MHz can be achieved.

The PCA9306 device does not provide any drive capability like the PCA9515 or PCA9517 series of devices. Therefore, higher-frequency applications require higher drive strength from the host side. No pullup resistor is needed on the host side (3.3 V) if the PCA9306 device is being driven by standard CMOS push-pull output driver. Ideally, it is best to minimize the trace length from the PCA9306 device on the sink side (1.8 V) to minimize signal degradation.

You can then use a simple formula to compute the maximum practical frequency component or the knee frequency (fknee). All fast edges have an infinite spectrum of frequency components. However, there is an inflection (or knee) in the frequency spectrum of fast edges where frequency components higher than fknee are insignificant in determining the shape of the signal.

To calculate fknee:

Equation 7. fknee= 0.5 / RT (10%–90%)
Equation 8. fknee = 0.4 / RT (20%–80%)

For signals with rise-time characteristics based on 10- to 90-percent thresholds, fknee is equal to 0.5 divided by the rise time of the signal. For signals with rise-time characteristics based on 20- to 80-percent thresholds, which is very common in many current device specifications, fknee is equal to 0.4 divided by the rise time of the signal.

Some guidelines to follow that help maximize the performance of the device:

  • Keep trace length to a minimum by placing the PCA9306 device close to the I2C output of the processor.
  • The trace length should be less than half the time of flight to reduce ringing and line reflections or non-monotonic behavior in the switching region.
  • To reduce overshoots, a pullup resistor can be added on the 1.8 V side; be aware that a slower fall time is to be expected.