JAJSH62O October   2004  – September 2023 PCA9306

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics AC Performance (Translating Down) (EN = 3.3 V)
    7. 6.7  Switching Characteristics AC Performance (Translating Down) (EN = 2.5 V)
    8. 6.8  Switching Characteristics AC Performance (Translating Up) (EN = 3.3 V)
    9. 6.9  Switching Characteristics AC Performance (Translating Up) (EN = 2.5 V)
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Definition of threshold voltage
      2. 8.1.2 Correct Device Set Up
      3. 8.1.3 Disconnecting an I2C target from the Main I2C Bus Using the EN Pin
      4. 8.1.4 Supporting Remote Board Insertion to Backplane with PCA9306
      5. 8.1.5 Switch Configuration
      6. 8.1.6 Controller on Side 1 or Side 2 of Device
      7. 8.1.7 LDO and PCA9306 Concerns
      8. 8.1.8 Current Limiting Resistance on VREF2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Enable (EN) Pin
      2. 8.3.2 Voltage Translation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 General Applications of I2C
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Bidirectional Voltage Translation
        2. 9.2.2.2 Sizing Pullup Resistors
        3. 9.2.2.3 PCA9306 Bandwidth
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 サポート・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14.   Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.2 Correct Device Set Up

In a normal set up shown in Figure 8-1, the enable pin and VREF2 are shorted together and tied to a 200-kΩ resistor, and a reference voltage equal to VREF1 plus the FET threshold voltage is established. This reference voltage is used to help pass lows from one side to another more effectively while still separating the different pull up voltages on both sides.

GUID-F75DD36F-8785-4415-A2AC-C6A5488E53F4-low.gifFigure 8-1 Normal Setup

Care should be taken to make sure VREF2 has an external resistor tied between it and VCC2. If VREF2 is tied directly to the VCC2 rail without a resistor, then there is no external resistance from the VCC2 to VCC1 to limit the current such as in Figure 8-2. This effectively looks like a low impedance path for current to travel through and potentially break the pass FET if the current flowing through the pass FET is larger than the absolute maximum continuous channel current specified in section 6.1. The continuous channel current is larger with a higher voltage difference between VCC1 and VCC2.

Figure 8-2 shows an improper set up. If VCC2 is larger than VCC1 but less than Vth, the impedance between VCC1 and VCC2 is high resulting in a low drain to source current, which does not cause damage to the device. Concern arises when VCC2 becomes larger than VCC1 by Vth. During this event, the NFET turns on and begin to conduct current. This current is dependent on the gate to source voltage and drain to source voltage.

GUID-EFBEDBA3-6B2F-4F34-9C2C-452462BFA7BA-low.gifFigure 8-2 Abnormal Setup