SLASE64A December 2014 – June 2017 PCM1860-Q1 , PCM1861-Q1 , PCM1862-Q1 , PCM1863-Q1 , PCM1864-Q1 , PCM1865-Q1
PRODUCTION DATA.
The PCM186x-Q1 powers the device using the pins shown in Figure 68.
The PCM186x-Q1 uses a combination of 3.3-V functional blocks and 1.8-V functional blocks to achieve high analog performance, combined with high levels of digital integration. As such, the device has three internal power rails. AVDD provides the analog circuits with a clean 3.3-V rail. DVDD is used for 3.3-V digital clock circuits. Externally, AVDD and DVDD can be connected together without significant impact to performance. The final rail, IOVDD, is used for driving the input/output digital circuitry.
The PCM186x-Q1 integrates an on-chip LDO to convert an external 3.3 V to the 1.8 V required by the digital core. The LDO input is derived from IOVDD. Power-supply pin descriptions are listed in Table 24.
NAME | DESCRIPTION |
---|---|
AVDD | Analog voltage supply (3.3 V) that powers the ADC, PGA, reference, and secondary ADC. |
DVDD | Digital voltage supply (3.3 V) that is used for the PLL and the oscillator circuit. |
IOVDD | Input/output pin voltage. Also used as a source for the internal LDO for the digital circuit. |
LDO | Output from the on-chip LDO that is used with a 0.1-µF decoupling capacitor. Can be driven (used as power input) with a 1.8-V supply to bypass the on-chip LDO for lower power consumption. |
AGND | Analog ground |
DGND | Digital ground |
All PCM186x-Q1 devices can support external devices with a 1.8 V I/O. This operating mode is configured by driving IOVDD and LDO with 1.8 V.
The PCM186x-Q1 devices do not have a brownout detector, or a reset pin to hold while the system is powering up. Make sure that the system design meets minimum AVDD, DVDD and IOVDD requirements.
The power-up sequence consists of the following steps:
To achieve the lowest levels of power down and sleep current, the following recommended write sequences are suggested on PCM186x-Q1 software-controlled devices:
Consumption as low as 0.59 mW
0x00=0x00 //select page0
0x70=0x14 //power down reference
0x00=0x03 //select page3
0x12=0x41 //disable OSC
0x00=0x00 //select page0
Consumption as low as 14 mW
Clocks must be running during this process
0x00=0x00 //select page0
0x70=0x72 //enter in sleep mode
0x00=0xfd //select page253
0x14=0x10 //change global bias current
0x00=0x00 //select page0
Now stop the clocks
Consumption as low as 11.15 mW
Clocks must be running during this process
0x00=0x00 //select page0
0x70=0x72 //enter in sleep mode
0x00=0xfd //select page253
0x14=0x10 //change global bias current
0x00=0x00 //select page0
stop the clocks (note: make sure the clock IO is 1.8 V)
This example shows the most typical usage. One single supply, shared between all three supply voltage inputs. Rail-connected decoupling capacitors are not shown. Figure 70 shows 3.3-V supply for all supplies. Figure 71 shows separate 3.3 V for AVDD and DVDD.
NOTE
There is no disadvantage in separating the AVDD and DVDD, as the device waits until both are present before powering up.
The PCM186x-Q1 also supports interfacing to lower power 1.8-V processors, as shown in Figure 72. In the presence of an external 1.8 V connected to LDO, the internal LDO that takes DVDD (3.3 V) and converts it to the 1.8-V core voltage is bypassed. Under such conditions, IOVDD will then be used as the 1.8-V source for the digital core of the device. In such systems, it is still important to have 3.3 V for DVDD, as specific sections of the digital core in the device run from 3.3 V.
This sequence is the final stage of the power up and is illustrated in Figure 73. After the PLL has locked, the ADC starts running, and the data follows the fade-in sequence according to the following steps: