SLASE64A December 2014 – June 2017 PCM1860-Q1 , PCM1861-Q1 , PCM1862-Q1 , PCM1863-Q1 , PCM1864-Q1 , PCM1865-Q1
PRODUCTION DATA.
The register map is the primary way to configure the PCM186x-Q1 software-controlled devices. The register map is separated into four pages: 0,1,3, and 253. Page 0 handles all of the device configuration. Page 1 is used to indirectly program coefficients into the two fixed function DSPs on the PCM186x-Q1. Page 3 and page 253 contain additional registers for lower-power use. All undocumented registers are considered reserved; do not write to undocumented registers.
Change pages by writing to register 0x00 with the required page.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PGA_VAL_CH1_L | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PGA_VAL_CH1_L | R/W | 0000 0000b | PGA Value Channel 1 Left Global channel gain for ADC1L. (analog + digital). Analog gain only, if manual gain mapping is enabled. (0x19) Specify two's complement value with 7.1 format. 1110 1000: –12.0 dB (Min) … 1111 1110: –1.0 dB 1111 1111: 0.5 dB 0000 0000: 0.0 dB (default) 0000 0001: 0.5 dB … 0000 0010: 1.0 dB … 0001 1000: 12.0 dB … 0010 1000: 20.0 dB … 0100 0000: 32.0 dB … 0101 0000: 40.0 dB (Max) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PGA_VAL_CH1_R | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PGA_VAL_CH1_R | R/W | 0000 0000b | PGA Value Channel 1 Right Programmable gain value, channel 1 right (see Page 0, 0x01 for complete description) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PGA_VAL_CH2_L | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PGA_VAL_CH2_L | R/W | 0000 0000b | PGA Value Channel 2 Left Programmable gain value, channel 2 left (see Page 0, 0x01 for complete description) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PGA_VAL_CH2_R | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | PGA_VAL_CH2_R | R/W | 0000 0000b | PGA Value Channel 2 Right Programmable gain value, channel 2 right (see Page 0, 0x01 for complete description) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SMOOTH | LINK | DPGA_CLIP_EN | MAX_ATT | START_ATT | AGC_EN | ||
R/W-1b | R/W-0b | R/W-0b | R/W-00b | R/W-11b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | SMOOTH | R/W | 1b |
PGA Control Enable PGA smooth change 0: Immediate change 1: Smooth change (default) |
6 | LINK | R/W | 0b | Link PGA Control 0: Independent control (default) 1: Ch1[R] / Ch2[L] / Ch2[R] follow Ch1[L] PGA value. |
5 | DPGA_CLIP_EN | R/W | 0b | Enable Clipping Detection After Digital PGA 0: Disable (default) 1: Enable |
4-3 | MAX_ATT | R/W | 00b | Attenuation Limit of the Automatic Clipping Suppression 00: –3 dB (default) 01: –4 dB 10: –5 dB 11: –6 dB |
2-1 | START_ATT | R/W | 11b | Start Automatic Clipping Suppression After Clipping is Detected CLIP_NUM Times 00: 80 01: 40 10: 20 11: 10 (default) |
0 | AGC_EN | R/W | 0b | Enable Automatic Clipping Suppression 0: Disable (default) 1: Enable |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL | RSV | SEL_L | |||||
R/W-0b | R/W-1b | R/W-00 0001b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | POL | R/W | 0b |
Change ADC1_INPUT_SEL_L Signal Polarity 0: Normal (default) 1: Inverted |
6 | RSV | R/W | 1b | Reserved. Always write 1. |
5-0 | SEL_L | R/W | 00 0001b | ADC 1 Input Channel Select (ADC1L) 00 0000: No select 00 0001: VINL1[SE] (default) 00 0010: VINL2[SE] 00 0011: VINL2[SE] + VINL1[SE] 00 0100: VINL3[SE] 00 0101: VINL3[SE] + VINL1[SE] 00 0110: VINL3[SE] + VINL2[SE] 00 0111: VINL3[SE] + VINL2[SE] + VINL1[SE] 00 1000: VINL4[SE] 00 1001: VINL4[SE] + VINL1[SE] 00 1010: VINL4[SE] + VINL2[SE] 00 1011: VINL4[SE] + VINL2[SE] + VINL1[SE] 00 1100: VINL4[SE] + VINL3[SE] 00 1101: VINL4[SE] + VINL3[SE] + VINL1[SE] 00 1110: VINL4[SE] + VINL3[SE] + VINL2[SE] 00 1111: VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE] 01 0000: {VIN1P, VIN1M}[DIFF] 10 0000: {VIN4P, VIN4M}[DIFF] 11 0000: {VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL | RSV | SEL_R | |||||
R/W-0b | R/W-1b | R/W-00 0001b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | POL | R/W | 0b |
Change ADC1_INPUT_SEL_R Signal Polarity 0: Normal (default) 1: Inverted |
6 | RSV | R/W | 1b | Reserved. Do not access. |
5-0 | SEL_R | R/W | 00 0001b | ADC 1 Input Channel Select (ADC1R) 00 0000: No select 00 0001: VINR1[SE] (default) 00 0010: VINR2[SE] 00 0011: VINR2[SE] + VINR1[SE] 00 0100: VINR3[SE] 00 0101: VINR3[SE] + VINR1[SE] 00 0110: VINR3[SE] + VINR2[SE] 00 0111: VINR3[SE] + VINR2[SE] + VINR1[SE] 00 1000: VINR4[SE] 00 1001: VINR4[SE] + VINR1[SE] 00 1010: VINR4[SE] + VINR2[SE] 00 1011: VINR4[SE] + VINR2[SE] + VINR1[SE] 00 1100: VINR4[SE] + VINR3[SE] 00 1101: VINR4[SE] + VINR3[SE] + VINR1[SE] 00 1110: VINR4[SE] + VINR3[SE] + VINR2[SE] 00 1111: VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE] 01 0000: {VIN2P, VIN2M}[DIFF] 10 0000: {VIN3P, VIN3M}[DIFF] 11 0000: {VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL | RSV | SEL_L | |||||
R/W-0b | R/W-1b | R/W-00 0010b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | POL | R/W | 0b |
Change ADC2_INPUT_SEL_L Signal Polarity 0: Normal (default) 1: Inverted |
6 | RSV | R/W | 1b | Reserved. Do not access. |
5-0 | SEL_L | R/W | 00 0010b | ADC 2 Input Channel Select (ADC2L) 00 0000: No select 00 0001: VINL1[SE] (default) 00 0010: VINL2[SE] 00 0011: VINL2[SE] + VINL1[SE] 00 0100: VINL3[SE] 00 0101: VINL3[SE] + VINL1[SE] 00 0110: VINL3[SE] + VINL2[SE] 00 0111: VINL3[SE] + VINL2[SE] + VINL1[SE] 00 1000: VINL4[SE] 00 1001: VINL4[SE] + VINL1[SE] 00 1010: VINL4[SE] + VINL2[SE] 00 1011: VINL4[SE] + VINL2[SE] + VINL1[SE] 00 1100: VINL4[SE] + VINL3[SE] 00 1101: VINL4[SE] + VINL3[SE] + VINL1[SE] 00 1110: VINL4[SE] + VINL3[SE] + VINL2[SE] 00 1111: VINL4[SE] + VINL3[SE] + VINL2[SE] + VINL1[SE] 01 0000: {VIN1P, VIN1M}[DIFF] 10 0000: {VIN4P, VIN4M}[DIFF] 11 0000: {VIN1P, VIN1M}[DIFF] + {VIN4P, VIN4M}[DIFF] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
POL | RSV | SEL_R | |||||
R/W-0b | R/W-1b | R/W-00 0010b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | POL | R/W | 0b |
Change ADC2_INPUT_SEL_R Signal Polarity 0: Normal (default) 1: Inverted |
6 | RSV | R/W | 1b | Reserved. Do not access. |
5-0 | SEL_R | R/W | 00 0010b | ADC 2 Input Channel Select (ADC2R) 00 0000: No select 00 0001: VINR1[SE] (default) 00 0010: VINR2[SE] 00 0011: VINR2[SE] + VINR1[SE] 00 0100: VINR3[SE] 00 0101: VINR3[SE] + VINR1[SE] 00 0110: VINR3[SE] + VINR2[SE] 00 0111: VINR3[SE] + VINR2[SE] + VINR1[SE] 00 1000: VINR4[SE] 00 1001: VINR4[SE] + VINR1[SE] 00 1010: VINR4[SE] + VINR2[SE] 00 1011: VINR4[SE] + VINR2[SE] + VINR1[SE] 00 1100: VINR4[SE] + VINR3[SE] 00 1101: VINR4[SE] + VINR3[SE] + VINR1[SE] 00 1110: VINR4[SE] + VINR3[SE] + VINR2[SE] 00 1111: VINR4[SE] + VINR3[SE] + VINR2[SE] + VINR1[SE] 01 0000: {VIN2P, VIN2M}[DIFF] 10 0000: {VIN3P, VIN3M}[DIFF] 11 0000: {VIN2P, VIN2M}[DIFF] + {VIN3P, VIN3M}[DIFF] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | SEL3 | ||||||
R/W-0000b | R/W-0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RSV | R/W | 0000b | Reserved. Do not access. |
3-0 | SEL | R/W | 0000b | Secondary ADC Input Channel Do not select the same channel that is already in use by an audio ADC 0: No Select (default) 1: ch1(L) 2: ch1(R) 3: ch2(L) 4: ch2(R) 5: ch3(L) 6: ch3(R) 7: ch4(L) 8: ch4(R) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_WLEN | RSV | TDM_LRCK_MODE | TX_WLEN | FMT | |||
R/W-01b | R/W-0 | R/W-0b | R/W-01b | R/W-00b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | TDM_OSEL | ||||||
R/W-000000b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RSV | R/W | 000000b | Reserved. Do not access. |
1-0 | TDM_OSEL | R/W | 00b | Select TDM Transmission Data Ch2 data only available on 4-channel device. 00: 2ch TDM (default) DOUT1: ch1[L], ch1[R] DOUT2: ch2[L], ch2[R] 01: 4ch TDM DOUT1: ch1[L], ch1[R], ch2[L], ch2[R] DOUT2: ch1[L], ch1[R], ch2[L], ch2[R] 10: 6ch TDM DOUT1: ch1[L], ch1[R], ch2[L], ch2[R], sec_ADC_LPF, sec_ADC_HPF DOUT2: ch1[L], ch1[R], ch2[L], ch2[R], sec_ADC_LPF, sec_ADC_HPF 11: RESERVED |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_TDM_OFFSET | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | TX_TDM_OFFSET | R/W | 0000 0000b |
Set Offset Position in Serial Audio Data Frame This setting is enabled when 0x0B FMT[1:0] is set to DSP format. 0: 0 (default) 1: 1 BCK (same as I2S) 2: 2 BCK 3: 3 BCK : 255: 255 BCK |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RX_TDM_OFFSET | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | RX_TDM_OFFSET | R/W | 0000 0000b |
Set Offset Position in a Serial Audio Data Frame This setting is enabled when I2S_RX_FMT is set to DSP format. Offset position in a serial audio data frame. 0: 0 (default) 1: 1 BCK (same as I2S, only if LRCK is configured as 50% duty cycle) 2: 2 BCK 3: 3 BCK : 255: 255 BCK |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DPGA_VAL_CH1_L | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DPGA_VAL_CH1_L | R/W | 0000 0000b | Gain Setting for Digital PGA Channel 1 Left 4-channel PCM186x-Q1 only when is used in following scenarios: i. Analog PGA gain and digital PGA are set separately. ii. Digital microphone Interface is used (when manual gain mapping is enabled in register 0x19). Specify two's complement value with 7.1 format. 0x28 to 0x3F in 0.5-dB steps Others: Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO1_POL | GPIO1_FUNC | GPIO0_POL | GPIO0_FUNC | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-001b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO3_POL | GPIO3_FUNC | GPIO2_POL | GPIO2_FUNC | ||||
R/W-0b | R/W-010b | R/W-0b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPIO3_POL | R/W | 0b | GPIO3 Polarity Control 0: Normal (default) 1: Invert |
6-4 | GPIO3_FUNC | R/W | 010b | Function select, GPIO1 000: GPIO3 001: Reserved 010: INT (default) 011: Internal SCK (Out) 100: Digital mute (In) 101: DOUT2 (Out) 110: DIN (In) 111: Reserved |
3 | GPIO2_POL | R/W | 0b | GPIO2 Polarity Control 0: Normal (default) 1: Invert |
2-0 | GPIO2_FUNC | R/W | 000b | Function select, GPIO2 000: GPIO2 (default) 001: Digital mic clock output 0 (Out) 010: INT 011: Internal SCK (Out) 100: Digital mute (In) 101: DOUT2 (Out) 110: DIN (In) 111: Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | GPIO1_DIR | RSV | GPIO0_DIR | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0b | Reserved. Do not access. |
6-4 | GPIO1_DIR | R/W | 000b | Direction Control of GPIO1 When Configured as GPIO Function 000: Input (default) 001: Input with sticky bit 010: Input with toggle detection 011: Raw input (not deglictched) 100: Output 101: Open drain 110: Reserved 111: Reserved |
3 | RSV | R/W | 0b | Reserved. Do not access. |
2-0 | GPIO0_DIR | R/W | 000b | Direction Control of GPIO0 When Configured as GPIO Function 000: Input (default) 001: Input with sticky bit 010: Input with toggle detection 011: Raw input (not deglictched) 100: Output 101: Open drain 110: Reserved 111: Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | GPIO3_DIR | RSV | GPIO2_DIR | ||||
R/W-0b | R/W-000b | R/W-0b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0b | Reserved. Do not access. |
6-4 | GPIO3_DIR | R/W | 000b | Direction Control of GPIO3 When Configured as GPIO Function 000: Input (default) 001: Input with sticky bit 010: Input with toggle detection 011: Raw input (not deglictched) 100: Output 101: Open drain 110: Reserved 111: Reserved |
3 | RSV | R/W | 0b | Reserved. Do not access. |
2-0 | GPIO2_DIR | R/W | 000b | Direction Control of GPIO2 When Configured as GPIO Function 000: Input (default) 001: Input with sticky bit 010: Input with toggle detection 011: Raw input (not deglictched) 100: Output 101: Open drain 110: Reserved 111: Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GPIO3_OUT | GPIO2_OUT | GPIO1_OUT | GPIO0_OUT | GPIO3_IN | GPIO2_IN | GPIO1_IN | GPIO0_IN |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GPIO3_OUT | R/W | 0b | GPIO3 Output Status |
6 | GPIO2_OUT | R/W | 0b | GPIO2 Output Status |
5 | GPIO1_OUT | R/W | 0b | GPIO1Output Status |
4 | GPIO0_OUT | R/W | 0b | GPIO0 Output Status |
3 | GPIO3_IN | R/W | 0b | GPIO3 Input Status or Toggle Status The sticky flag is cleared when this register is read. |
2 | GPIO2_IN | R/W | 0b | GPIO2 Input Status or Toggle Status The sticky flag is cleared when this register is read. |
1 | GPIO1_IN | R/W | 0b | GPIO1 Input Status or Toggle Status The sticky flag is cleared when this register is read. |
0 | GPIO0_IN | R/W | 0b | GPIO0 Input Status or Toggle Status The sticky flag is cleared when this register is read. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PULL_DOWN_DIS[3] | PULL_DOWN_DIS[2] | PULL_DOWN_DIS[1] | PULL_DOWN_DIS[0] | RSV | |||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PULL_DOWN_DIS[3] | R/W | 0b | Enable or Disable the Pull-Down Resistor of GPIO3 0: Enable the pull down of GPIO3, IntC (pin 19) 1: Disable the pull down |
6 | PULL_DOWN_DIS[2] | R/W | 0b | Enable or Disable the Pull-Down Resistor of GPIO2 0: Enable the pull down of GPIO2, IntB (pin 20) |
5 | PULL_DOWN_DIS[1] | R/W | 0b | Enable or Disable the Pull-Down Resistor of GPIO1 0: Enable the pull down of GPIO1 (pin 21) 1: Disable the pull down |
4 | PULL_DOWN_DIS[0] | R/W | 0b | Enable or Disable the Pull-Down Resistor of GPIO0 0: Enable the pull down of GPIO0 (pin 22) 1: Disable the pull down |
3-0 | RSV | R/W | 0b | Reserved. Do not access. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DPGA_VAL_CH1_R | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DPGA_VAL_CH1_R | R/W | 0000 0000b | Gain Setting for Digital PGA Channel 1 Right 4-channel PCM186x-Q1 only when is used in following scenarios: i. Analog PGA gain and digital PGA are set separately ii. Digital microphone Interface is used (\when manual gain mapping is enabled in register 0x19) Specify two's complement value with 7.1 format. 0010 1000: 0.0 dB 0010 1001: 0.5 dB 0010 1010: 1.0 dB 0010 1011: 1.5 dB : 0011 1111: 7.5 dB (max) Others: Reserved |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DPGA_VAL_CH2_L | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DPGA_VAL_CH2_L | R/W | 0000 0000b | Gain Setting for Digital PGA Channel 2 Left 4-channel PCM186x-Q1 only. See Page 0, Reg 0x16 description |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DPGA_VAL_CH2_R | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DPGA_VAL_CH2_R | R/W | 0000 0000b | Gain Setting for Digital PGA channel 2 Right 4-channel PCM186x-Q1 only. See Page 0, Reg 0x16 description |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DPGA_CH2_R | DPGA_CH2_L | DPGA_CH1_R | DPGA_CH1_L | APGA_CH2_R | APGA_CH2_L | APGA_CH1_R | APGA_CH1_L |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIGMIC_IN1_SEL | DIGMIC_IN0_SEL | RSV | DIGMIC_4CH | DIGMIC_EN | |||
R/W-00b | R/W-00b | R/W-00b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | DIGMIC_IN1_SEL | R/W | 00b | Digital Mic Data Input Selection for MIC1 Interface (4-channel devices only) 00: GPIO0 (default) 01: GPIO1 10: Invalid 11: Invalid |
5-4 | DIGMIC_IN0_SEL | R/W | 00b | Digital Mic Data Input Selection for MIC0 Interface 00: GPIO0 (default) 01: GPIO1 10: Invalid 11: Invalid |
3-2 | RSV | R/W | 00b | Reserved. Do not access. |
1 | DIGMIC_4CH | R/W | 0b | Second Pair of Filters Selection for Digital Microphone as Signal Processing (4-channel device only) 0: configured for analog ADC signal processing (default) 1: configured for digital MIC signal processing |
0 | DIGMIC_EN | R/W | 0b | First Pair of Filters Selection for Digital Microphone as Signal Processing 0: configured as analog ADC signal processing (default) 1: configured as digital MIC signal processing |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DIN_RESAMP | ||||||
R/W-00 0000b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-2 | RSV | R/W | 00 0000b | Reserved. Do not access. |
1-0 | DIN_RESAMP | R/W | 00b | Resample DIN with Internal BCK to Avoid Internal Timing Issue 00: No resample (default) 01: resample DIN with rising edge of BCK 10: resample DIN with falling edge of BCK 11: Not supported |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SCK_XI_SEL | MST_SCK_SRC | MST_MODE | ADC_CLK_SRC | DSP2_CLK_SRC | DSP1_CLK_SRC | CLKDET_EN | |
R/W-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | SCK_XI_SEL | R/W | 00b | SCK or XTAL Selection 00: SCK or XTAL (default) 01: SCK 10: XTAL 11: Reserved |
5 | MST_SCK_SRC | R/W | 0b | Master-Mode SCK Source Selection 0: SCK or XI (default) 1: PLL (as in BCK PLL mode) |
4 | MST_MODE | R/W | 0b | Master or Slave Selection 0: Slave (default) 1: Master |
3 | ADC_CLK_SRC | R/W | 0b | ADC Clock Source Selection (ignored if CLKDET_EN = 1) 0: SCK (default) 1: PLL |
2 | DSP2_CLK_SRC | R/W | 0b | DSP2 Clock Source Selection (ignored if CLKDET_EN = 1) 0: SCK (default) 1: PLL |
1 | DSP1_CLK_SRC | R/W | 0b | DSP1 Clock Source Selection (ignored if CLKDET_EN = 1) 0: SCK (default) 1: PLL |
0 | CLKDET_EN | R/W | 1b | Enable Auto Clock Detector Configuration 0: Disable 1: Enable (default) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DIV_NUM | ||||||
R/W-0b | R/W-000 0000b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DIV_NUM | ||||||
R/W-0b | R/W-000 0001b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0b | Reserved. Do not access. |
6-0 | DIV_NUM | R/W | 000 0001b | Set DSP2 Clock Divider Value Ignored if CLKDET_EN = 1 0: 1 1: 1/2 (default) 2: 1/3 3: 1/4 : 127: 1/128 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DIV_NUM | ||||||
R/W-0b | R/W-000 0011b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0 | Reserved. Do not access. |
6-0 | DIV_NUM | R/W | 000 0011b | Set ADC Clock Divider Value Ignored if CLKDET_EN = 1 0: 1 1: 1/2 2: 1/3 3: 1/4 (default) : 127: 1/128 |
CLK_DIV_PLL_SCK is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DIVNUM | ||||||
R/W-0b | R/W-000 0111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0 | Reserved. Do not access. |
6-0 | DIV_NUM | R/W | 000 0111b | Set PLL SCK Clock Output Divider for SCK Out (when enabled) Used in BCK slave mode or master mode where PLL-ed SCK Out is required. Requires MST_SCK_SRC (0x20) to be enabled. Divider value: 0: 1 1: 1/2 2: 1/3 3: 1/4 : 7: 1/8 (default) : 127: 1/128 |
CLK_DIV_SCK_BCK is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DIVNUM | ||||||
R/W-0b | R/W-000 0011b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0 | Reserved. Do not access. |
6-0 | DIV_NUM | R/W | 000 0011b | Set Master Clock (SCK) to BCK Divider Value Ratio of master clock (SCK) to bit clock (BCK) in master mode Divider value: 0: 1 1: 1/2 2: 1/3 3: 1/4 (default) : 7: 1/8 : 127: 1/128 |
CLK_DIV_BCK_LRCK is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIV_NUM | |||||||
R/W-0011 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIV_NUM | R/W | 0011 1111b | Set the Master SCK Clock Value SCK to LRCK ratio in master mode Divider value: 0: 1 1: 1/2 2: 1/3 3: 1/4 : 63: 1/64 (default) : 127: 1/128 : 255: 1/256 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | LOCK | RSV | PLL_REF_SEL | PLL_EN | |||
R/W-000b | R/W-0b | R/W-00b | R/W-0b | R/W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RSV | R/W | 000b | Reserved. Do not access. |
4 | LOCK | R/W | 0b | PLL Lock Status 0: Not locked (default) 1: Locked |
3-2 | RSV | R/W | 00b | Reserved. Do not access. |
1 | PLL_REF_SEL | R/W | 0b | PLL Reference Clock Selection Ignored if CLKDET_EN = 1 0: SCK (default) 1: BCK |
0 | PLL_EN | R/W | 1b | PLL Enable Ignored if CLKDET_EN = 1 0: Disable 1: Enable (default) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | P | ||||||
R/W-0b | R/W-000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0b | Reserved. Do not access. |
6-0 | R/W | 000 0000b | PLL P Divider Value Ignored if CLKDET_EN = 1 0: 1 (default) 1: 1/2 2: 1/3 3: 1/4 : 127: 1/128 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | R | ||||||
R/W-0000b | R/W-0000b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | J | ||||||
R/W-0b | R/W-000 0001b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
D_LSB | |||||||
R/W-0000 0000b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | D_MSB | ||||||
R/W-00b | R/W-00 0000b |
SIGDET_CH_MODE is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4R | CH4L | CH3R | CH3L | CH2R | CH2L | CH1R | CH1L |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH4R | R/W | 0b | Signal Detection Mode for Channel 4 Right Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
6 | CH4L | R/W | 0b | Signal Detection Mode for Channel 4 Left Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
5 | CH3R | R/W | 0b | Signal Detection Mode for Channel 3 Right Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
4 | CH3L | R/W | 0b | Signal Detection Mode for Channel 3 Left Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
3 | CH2R | R/W | 0b | Signal Detection Mode for Channel 2 Right Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
2 | CH2L | R/W | 0b | Signal Detection Mode for Channel 2 Left Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
1 | CH1R | R/W | 0b | Signal Detection Mode for Channel 1 Right Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
0 | CH1L | R/W | 0b | Signal Detection Mode for Channel 1 Left Select the signal detection mode for each channel in SLEEP mode 0: Audio signal detection (default) 1: DC level-change detection |
SIGDET_TRIG_MASK is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4R | CH4L | CH3R | CH3L | CH2R | CH2L | CH1R | CH1L |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH4R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 4 Right All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
6 | CH4L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 4 Left All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
5 | CH3R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 3 Right All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
4 | CH3L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 3 Left All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
3 | CH2R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 2 Right All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
2 | CH2L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 2 Left All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
1 | CH1R | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 1 Right All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
0 | CH1L | R/W | 0b | Mask Bits of Interrupt Trigger for Channel 1 Left All channels are scanned, even if they are masked. Developers can ignore specific channels and prevent them from generating interrupts using this register 0: No mask (default) 1: Mask |
SIGDET_STAT is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CH4R | CH4L | CH3R | CH3L | CH2R | CH2L | CH1R | CH1L |
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | CH4R | R/W | 0b | Status of Signal Level Detection in Both Energysense and Controlsense Modes (read only). Field column indicates respective channel. A) In audio signal detection mode: a) In the active or run state: 0: Signal active 1: Signal lost b) In the sleep mode 0: Signal lost 1: Signal active In automatic clipping suppression mode: 0: No change 1: changed DC level |
6 | CH4L | R/W | 0b | |
5 | CH3R | R/W | 0b | |
4 | CH3L | R/W | 0b | |
3 | CH2R | R/W | 0b | |
2 | CH2L | R/W | 0b | |
1 | CH1R | R/W | 0b | |
0 | CH1L | R/W | 0b |
SIGDET_LOSS_TIME is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | TIME | ||||||
R/W-000b | R/W-0 0001b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RSV | R/W | 000 | Reserved. Do not access. |
4-0 | TIME | R/W | 0 0001b | If the signal drops below the threshold on the current audio input for this set amount of time, the device generates an interrupt 0: Prohibit 1: 1 minute (default) 2: 2 minutes 3: 3 minutes : 30: 30 minutes (Max) |
SIGDET_SCAN_TIME is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | TIME | ||||||
R/W-0 0000b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-33 | RSV | R/W | 0 0000 | Reserved. Do not access. |
2-1 | TIME | R/W | 000 | Configures the scan time for each channel in the SLEEP state 000: 160 ms (default) 001: 80 ms 010: 40 ms 011: 20 ms 100: 10 ms Others: Invalid |
SIGDET_INT_INTVL is the alternate for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | RSV | RSV | RSV | RSV | INT_INTVL | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RSV | R/W | 0 0000 | Reserved. Do not access. |
2-0 | INT_INTVL | R/W | 001b | Interval time of the signal detector interrupt when there is signal detection. This time value is used for energysense wakeup from sleep interrupt and from controlsense interrupts Interval time of the signal-resume interrupt 000: No repeat 001: 1 sec (default) 010: 2 sec 011: 3 sec 100: 4 sec Others: Invalid |
SIGDET_DC_REF_CH1_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH1_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
SIGDET_DC_LEVEL_CH1_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
SIGDET_DC_REF_CH1_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH1_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
SIGDET_DC_LEVEL_CH 1_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
SIGDET_DC_REF_CH2_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH2_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
SIGDET_DC_LEVEL_CH2_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
SIGDET_DC_REF_CH2_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH2_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
SIGDET_DC_LEVEL_CH 2_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
SIGDET_DC_REF_CH3_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH3_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
SIGDET_DC_LEVEL_CH3_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
SIGDET_DC_REF_CH3_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH3_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
SIGDET_DC_LEVEL_CH3_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
SIGDET_DC_REF_CH4_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH4_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
SIGDET_DC_LEVEL_CH4_L is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
SIGDET_DC_REF_CH4_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REF | |||||||
R/W-1000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | REF | R/W | 1000 0000b | Reference Level of Controlsense Detection |
SIGDET_DC_DIFF_CH4_R is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DIFF | |||||||
R/W-0111 1111b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | DIFF | R/W | 0111 1111b | Difference Level of Controlsense Detection |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LEVEL | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | LEVEL | R | 0000 0000b | Current DC Level |
AUXADC_DATA_CTRL is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DC_NOLATCH | AUXADC_RDY | DC_RDY | AUXADC_LATCH | AUXADC_DATA_TYPE | DC_CH | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | DC_NOLATCH | R/W | 0b | Read Without Latch Read directly without latch operation (from secondary ADC) 0: With latch operation (default) 1: Without latch operation when read dc value |
6 | AUXADC_RDY | R/W | 0b | AUXADC Ready Indicate latch operation is finished and AUXADC value is ready for read operation. 0: Latch operation is running (default) 1: AUXADC value is ready for read operation |
5 | DC_RDY | R/W | 0b | DC Ready Indicate latch operation is finished and dc value is ready. 0: Latch operation is running (default) 1: DC value is ready for read operation |
4 | AUXADC_LATCH | R/W | 0b | AUXADC Latch Trigger to latch 16-bit AUXADC value for read operation: rising edge is the trigger signal 0: Idle (default) 1: Latch the value for read operation |
3 | AUXADC_DATA_TYPE | R/W | 0b | Data to be Read From Control Interface 0: read LPF data (default) 1: read HPF data |
2-0 | DC_CH[2:0] | R/W | 000b | DC-Value Channel Select Select dc-value channel to be latched for control-interface read operation 000: CH1_L (default) 001: CH1_R 010: CH2_L 011: CH2_R 100: CH3_L 101: CH3_R 110: CH4_L 111: CH4_R |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUXADC_DATA_LSB | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | AUXADC_DATA_LSB | R | 0000 0000b | Low Byte of Secondary ADC Output The data depends on AUXADC_DATA_TYPE setting AUXADC_DATA_TYPE = 0: reading LPF of secondary ADC AUXADC_DATA_TYPE = 1: reading HPF of secondary ADC |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
AUXADC_DATA_MSB | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | AUXADC_DATA_MSB | R | 0000 0000b | High Byte of Secondary ADC Output [15:8] The data depends on AUXADC_DATA_TYPE setting AUXADC_DATA_TYPE = 0: reading LPF of secondary ADC AUXADC_DATA_TYPE = 1: reading HPF of secondary ADC |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | POSTPGA_CP | RSV | DC_CHANG | DIN_TOGGLE | ENGSTR | ||
R/W-000b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-1b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | POSTPGA_CP | RSV | DC_CHANG | DIN_TOGGLE | ENGSTR | ||
R-000b | R-0b | R-0b | R-0b | R-0b | R-0b |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | POL | RSV | WIDTH | ||||
R/W-00b | R/W-01b | R/W-00b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RSV | R/W | 00b | Reserved. Always write 00b. |
5-4 | POL | R/W | 01b | Polarity of the Interrupt Pulse 00: Low active 01: High active (default) 10: Open drain (L-Active) 11: Reserved |
3-2 | RSV | R/W | 00b | Reserved. Always write 00b. |
1-0 | WIDTH | R/W | 00b | Width of the Interrupt Pulse 00: 1 ms (default) 01: 2 ms 10: 3 ms 11: Infinity for level sense |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | PWRDN | SLEEP | STBY | ||||
R/W-0 1110b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RSV | R/w | 0 1110b | Reserved. Always write 0 1110b |
2 | PWRDN | R/W | 0b | Enter Analog Power Down State 0: Power Up (default) 1: Power Down |
1 | SLEEP | R/W | 0b | Enter the Device Sleep State After the chip enters SLEEP state, energysense application will be triggered. 0: Power Up (default) 1: Sleep |
0 | STBY | R/W | 0b | Enter Digital Standby State 0: Run (default) 1: Standby |
DSP_CTRL is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
2CH | RSV | FLT | HPF_EN | MUTE_CH2_R | MUTE_CH2_L | MUTE_CH1_R | MUTE_CH1_L |
R/W-0b | R/W-0b | R/W-0b | R/W-1b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 2CH | R/W | 0b | Processing Mode Selection Select the processing mode for 4-channel device only. This configuration CANNOT be changed on the fly in RUN state. 0: 4 channels (default) 1: 2 channels |
6 | RSV | R/W | 0b | Reserved. Always write 0b. |
5 | FLT | R/W | 0b | Select Decimation Filter Type 0: Normal (default) 1: Short latency |
4 | HPF_EN | R/W | 1b | Enable High-Pass Filter 0: Disable 1: Enable (default) |
3 | MUTE_CH2_R | R/W | 0b | Mute Ch2(R) 0: Unmute (default) 1: Mute |
2 | MUTE_CH2_L | R/W | 0b | Mute Ch2(L) 0: Unmute (default) 1: Mute |
1 | MUTE_CH1_R | R/W | 0b | Mute Ch1(R) 0: Unmute (default) 1: Mute |
0 | MUTE_CH1_L | R/W | 0b | Mute Ch1(L) 0: Unmute (default) 1: Mute |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | STATE | ||||||
R-0000b | R-0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-4 | RSV | R | 0000b | Reserved. Always write 0000b. |
3-0 | STATE | R | 0000b | Device Current Status 0000: Power down (default) 0001: Wait clock stable 0010: Release reset 0011: Stand-by 0100: Fade IN 0101: Fade OUT 0110: Reserved 0111: Reserved 1000: Reserved 1001: Sleep 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: Run |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | INFO | ||||||
R-0 0000b | R-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RSV | R | 0 0000b | Reserved. Always write 0 0000b. |
2-0 | INFO | R | 000b | Current Sampling Frequency 000: Out of range (Low) or LRCK Halt (default) 001: 8 kHz 010: 16 kHz 011: 32 khz to 48 kHz 100: 88.2 kHz to 96 kHz 101: 176.4 kHz to 192 kHz 110: Out of range (High) 111: Invalid fS |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | BCK_RATIO | RSV | SCK_RATIO | ||||
R-0b | R-000b | R-0b | R-000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R | 0b | Reserved. Always write 0 0000b. |
6-4 | BCK_RATIO | R | 000b | Current Receiving BCK Ratio Default value: 000 (default) 000: Out of range (L) or BCK Halt 001: 32 010: 48 011: 64 100: 256 101: (Not assigned) 110: Out of range (H) 111: Invalid BCK ratio or LRCK Halt |
3 | RSV | R | 0b | Reserved. Always write 0 0000b. |
2-0 | SCK_RATIO | R | 000b | Current SCK Ratio 000: Out of range (L) or SCK Halt (default) 001: 128 010: 256 011: 384 100: 512 101: 768 110: Out of range (H) 111: Invalid SCK ratio or LRCK Halt |
CLK_ERR_STAT is the alternate name for this register.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | LRCKHLT | BCKHLT | SCKHTL | RSV | LRCKERR | BCKERR | SCKERR |
R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R | 0b | Reserved. Always write 0b. |
6 | LRCKHLT | R | 0b | LRCK Halt Status 0: No Error (default) 1: Halt |
5 | BCKHLT | R | 0b | BCK Halt Status 0: No Error (default) 1: Halt |
4 | SCKHTL | R | 0b | SCK Halt Status 0: No Error (default) 1: Halt |
3 | RSV | R | 0b | Reserved. Always write 0b. |
2 | LRCKERR | R | 0b | LRCK Error Status 0: No Error (default) 1: Error |
1 | BCKERR | R | 0b | BCK Error Status 0: No Error (default) 1: Error |
0 | SCKERR | R | 0b | SCK Error Status 0: No Error (default) 1: Error |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DVDD | AVDD | LDO | ||||
R/W-0b | R/W-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-3 | RSV | R | 0 0000b | Reserved. Always write 0 0000b. |
2 | DVDD | R | 0b | DVDD Status 0:Bad or Missing (default) 1:Good |
1 | AVDD | R | 0b | AVDD Status 0:Bad or issing (default) 1:Good |
0 | LDO | R | 0b | Digital LDO Status 0:Bad or Missing (default) 1:Good |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | DONE | RSV | BUSY | R_REQ | W_REQ | ||
R/W-000b | R-0b | R/W-0b | R-0b | R/W-0b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RSV | R/W | 000b | Reserved. Always write 000b. |
4 | DONE | R | 0b | Done Status Flag 1: Write or read operation is done with one cycle as indicator 0: Idle or is busy (default) |
3 | RSV | R/W | 0b | Reserved. Always write 000b. |
2 | BUSY | R | 0b | Busy Status Flag 1: Write or read operation is running and not finished 0: Write or read operation is finished (default) |
1 | R_REQ | R/W | 0b | Memory Mapper Register Access to DSP-2 - READ 1: Request read operation 0: The read operation is done and data is ready to read from I2C/SPI interface (default) |
0 | W_REQ | R/W | 0b | Memory Mapper Register Access to DSP-2 - WRITE 1: Request write operation 0: The write operation is done and is ready for next write operation command (default) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | MEM_ADDR | ||||||
R/W-0b | R/W-000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | RSV | R/W | 0b | Reserved. Always write 0b. |
6-0 | MEM_ADDR | R/W | 000 0000b | Memory Mapped Register Address Status of the memory mapped register access |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_WDATA_0 | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MEM_WDATA_0 | R/W | 0000 0000b | Write Data to 24-Bit Memory Coefficient [23:16] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_WDATA_1 | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MEM_WDATA_1 | R/W | 0000 0000b | Write Data to 24-Bit Memory Coefficient [15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_WDATA_2 | |||||||
R/W-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MEM_WDATA_2 | R/W | 0000 0000b | Write Data to 24-Bit Memory Coefficient [7:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_WDATA_3 | RSV | ||||||
R/W-0b | R/W-000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MEM_WDATA_2 | R/W | 0b | Write Data to 24-Bit Memory Reserved |
6-0 | RSV | R/W | 000 0000b | Reserved. Always write 000 0000b. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_RDATA_0 | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MEM_RDATA_0 | R | 0000 0000b | Read Data from 24-Bit Memory Coefficient [23:16] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_RDATA_1 | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MEM_RDATA_1 | R | 0000 0000b | Read Data from 24-Bit Memory Coefficient [15:8] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_RDATA_2 | |||||||
R-0000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-0 | MEM_RDATA_2 | R | 0000 0000b | Read Data from 24-Bit Memory Coefficient [7:0] |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_RDATA_3 | RSV | ||||||
R/W-0b | R/W-000 0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | MEM_RDATA_3 | R | 0b | Read Data from 24-Bit Memory Reserved |
6-0 | RSV | R/W | 000 0000b | Reserved. Always write 000 0000b. |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | PD | ||||||
R/W-010 0000b | R/W-0b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-1 | RSV | R/W | 010 0000b | Reserved. Always write 010 0000b |
0 | PD | R/W | 0b | Oscillator Power Down Control 0: Power up (default) 1: Power down |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RSV | TERM | RSV | PDZ | ||||
R/W-000b | W-0b | R/W-000b | W-1b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | RSV | R/W | 000b | Reserved. Always write 000b. |
4 | TERM | W | 0b | Mic Bias Resistor Bypass (Write only) 0: Disable (default) 1: Enable |
3-1 | RSV | R/W | 000b | Reserved. Always write 000b. |
0 | PDZ | W | 0b | Mic Bias Control (Write only) 0: Power down 1: Power up (default) |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PGA_ICI | REF_ICI | RSV | |||||
R/W-00b | R/W-00b | R/W-0000b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | PGA_ICI | R/W | 00b | PGA Bias Current Trim 00: 100% (default) 01: Reserved 10: 75% 11: Reserved |
5-4 | REF_ICI | R/W | 00b | Global bias current trim 00: 100% (default) 01: 75% 10: Reserved 11: Reserved |
3-0 | RSV | R/W | 0000b | Reserved. Always write 0000b. |