The SN6505x-Q1 has a CLK pin which can be used to synchronize the device with system clock and in turn with other SN6505x-Q1 devices so that the system can control the exact switching frequency of the device. The Rising edge of the CLK is used to divide a clock by two and used to drive the gates. Figure 41 shows the timing diagram for the same. The device also has external clock fail safe feature which automatically switches the device to the internal clock if a valid input clock is not present for long (tCLKTIMER). The in-built emissions reduction scheme of Spread Spectrum clocking is disabled when external clock is present.