JAJSL15N July   1997  – April 2021 SN55LVDS31 , SN65LVDS31 , SN65LVDS3487 , SN65LVDS9638

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings #GUID-35E89C88-1E48-404C-8AB6-22CCA817C2ED/SLLS2613609
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: SN55LVDS31
    6. 7.6 Electrical Characteristics: SN65LVDSxxxx
    7. 7.7 Switching Characteristics: SN55LVDS31
    8. 7.8 Switching Characteristics: SN65LVDSxxxx
    9. 7.9 Typical Characteristics
      1. 7.9.1 17
  8. 8 Parameter Measurement Information
    1. 8.1 19
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Driver Disabled Output
      2. 9.3.2 NC Pins
      3. 9.3.3 Unused Enable Pins
      4. 9.3.4 Driver Equivalent Schematics
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Point-to-Point Communications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Driver Supply Voltage
          2. 10.2.1.2.2 Driver Bypass Capacitance
          3. 10.2.1.2.3 Driver Output Voltage
          4. 10.2.1.2.4 Interconnecting Media
          5. 10.2.1.2.5 PCB Transmission Lines
          6. 10.2.1.2.6 Termination Resistor
          7. 10.2.1.2.7 Driver NC Pins
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Multidrop Communications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Interconnecting Media
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 49
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Microstrip vs. Stripline Topologies
      2. 12.1.2 Dielectric Type and Board Construction
      3. 12.1.3 Recommended Stack Layout
      4. 12.1.4 Separation Between Traces
      5. 12.1.5 Crosstalk and Ground Bounce Minimization
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Other LVDS Products
    2. 13.2 Documentation Support
      1. 13.2.1 Related Information
      2. 13.2.2 ドキュメントの更新通知を受け取る方法
      3. 13.2.3 Related Links
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PW|16
  • NS|16
  • D|16
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

GUID-4134AA19-9FFA-41D9-9A05-AC8940C30A17-low.gif
Table 6-1 Pin Functions: SN55LVDS31 J or W, SN65LVDS31 D or PW
PIN I/O DESCRIPTION
NAME NUMBER
VCC 16 – Supply voltage
GND 8 – Ground
1A 1 I LVTTL input signal
1Y 2 O Differential (LVDS) non-inverting output
1Z 3 O Differential (LVDS) inverting output
2A 7 I LVTTL input signal
2Y 6 O Differential (LVDS) non-inverting output
2Z 5 O Differential (LVDS) inverting output
3A 9 I LVTTL input signal
3Y 10 O Differential (LVDS) non-inverting output
3Z 11 O Differential (LVDS) inverting output
4A 15 I LVTTL input signal
4Y 14 O Differential (LVDS) non-inverting output
4Z 13 O Differential (LVDS) inverting output
G 4 I Enable (HI = ENABLE)
G/ 12 I Enable (LO = ENABLE)
Table 6-2 Pin Functions: SN65LVDS31FK
PIN I/O DESCRIPTION
NAME NUMBER
VCC 20 – Supply voltage
GND 10 – Ground
1A 2 I LVTTL input signal
1Y 3 O Differential (LVDS) non-inverting output
1Z 4 O Differential (LVDS) inverting output
2A 9 I LVTTL input signal
2Y 8 O Differential (LVDS) non-inverting output
2Z 7 O Differential (LVDS) inverting output
3A 12 I LVTTL input signal
3Y 13 O Differential (LVDS) non-inverting output
3Z 14 O Differential (LVDS) inverting output
4A 19 I LVTTL input signal
4Y 18 O Differential (LVDS) non-inverting output
4Z 17 O Differential (LVDS) inverting output
G 5 I Enable (HI = ENABLE)
G/ 15 I Enable (LO = ENABLE)
NC 1, 6, 11, 16 – No connection
Table 6-3 Pin Functions: SN65LVDS3487D
PIN I/O DESCRIPTION
NAME NUMBER
VCC 16 – Supply voltage
GND 8 – Ground
1A 1 I LVTTL input signal
1Y 2 O Differential (LVDS) non-inverting output
1Z 3 O Differential (LVDS) inverting output
2A 7 I LVTTL input signal
2Y 6 O Differential (LVDS) non-inverting output
2Z 5 O Differential (LVDS) inverting output
3A 9 I LVTTL input signal
3Y 10 O Differential (LVDS) non-inverting output
3Z 11 O Differential (LVDS) inverting output
4A 15 I LVTTL input signal
4Y 14 O Differential (LVDS) non-inverting output
4Z 13 O Differential (LVDS) inverting output
1,2EN 4 I Enable for channels 1 and 2
3,4EN 12 I Enable for channels 3 and 4
Table 6-4 Pin Functions: SN65LVDS9638D, SN65LVDS9638DGN, SN65LVDS9638DGK
PIN I/O DESCRIPTION
NAME NUMBER
VCC 1 – Supply voltage
GND 4 – Ground
1A 2 I LVTTL input signal
1Y 8 O Differential (LVDS) non-inverting output
1Z 7 O Differential (LVDS) inverting output
2A 3 I LVTTL input signal
2Y 6 O Differential (LVDS) non-inverting output
2Z 5 O Differential (LVDS) inverting output