JAJSOS8C September 2013 – June 2022 SN74LV1T00
Signals can be translated down using the SN74LV1T00. The voltage applied at the VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state. Ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 9-2.
For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to match 1.8 V CMOS signals when operating from 1.8-V VCC. See Figure 9-3.
Down Translation Combinations:
1.8-V VCC – Inputs from 2.5 V, 3.3 V, and 5.0 V
2.5-V VCC – Inputs from 3.3 V and 5.0 V
3.3-V VCC – Inputs from 5.0 V