JAJSOS8C
September 2013 – June 2022
SN74LV1T00
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Related Products
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Switching Characteristics
7.7
Operating Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Clamp Diode Structure
9.3.2
Balanced CMOS Push-Pull Outputs
9.3.3
LVxT Enhanced Input Voltage
9.3.3.1
Down Translation
9.3.3.2
Up Translation
9.4
Device Functional Modes
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
サポート・リソース
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
DCK|5
MPDS025H
DBV|5
MPDS018S
サーマルパッド・メカニカル・データ
発注情報
jajsos8c_oa
jajsos8c_pm
7.8
Typical Characteristics
Figure 7-1
Excellent Signal Integrity
(1.8 V to 3.3 V at 3.3-V V
CC
)
Figure 7-3
Excellent Signal Integrity
(3.3 V to 1.8 V at 1.8-V V
CC
)
Figure 7-2
Excellent Signal Integrity
(3.3 V to 3.3 V at 3.3-V V
CC
)