JAJSDI7C July   2017  – February 2022 TAS2505-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2S/LJF/RJF Timing in Master Mode
    7. 6.7  I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  DSP Timing in Master Mode
    9. 6.9  DSP Timing in Slave Mode
    10. 6.10 I2C Interface Timing
    11. 6.11 SPI Interface Timing
    12. 6.12 Typical Characteristics
      1. 6.12.1 Class D Speaker Driver Performance
      2. 6.12.2 HP Driver Performance
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Audio Analog I/O
      2. 7.3.2 Audio DAC and Audio Analog Outputs
      3. 7.3.3 DAC
      4. 7.3.4 POR
      5. 7.3.5 CLOCK Generation and PLL
      6. 7.3.6 Speaker Driver
      7. 7.3.7 Automotive Diagnostics
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Pins
      2. 7.4.2 Analog Pins
      3. 7.4.3 Multifunction Pins
      4. 7.4.4 Analog Signals
        1. 7.4.4.1 Analog Inputs AINL and AINR
      5. 7.4.5 DAC Processing Blocks — Overview
      6. 7.4.6 Digital Mixing and Routing
      7. 7.4.7 Analog Audio Routing
      8. 7.4.8 Digital Audio and Control Interface
        1. 7.4.8.1 Digital Audio Interface
        2. 7.4.8.2 Control Interface
          1. 7.4.8.2.1 I2C Control Mode
          2. 7.4.8.2.2 SPI Digital Interface
        3. 7.4.8.3 Device Special Functions
    5. 7.5 Register Map
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Configuration
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Pad
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGE|24
サーマルパッド・メカニカル・データ
発注情報

Multifunction Pins

Table 7-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).

Table 7-1 Multifunction Pin Assignments
1234567
PIN FUNCTIONMCLKBCLKWCLKDINGPIO
/DOUT
SCLKMISO
APLL InputS(2)S(3)ES(4)
BCodec Clock InputS(2),D(5)S(3)S(4)
CI2S BCLK inputS(3),D
DI2S BCLK outputE(1)
EI2S WCLK inputE, D
FI2S WCLK outputE
GI2S DINE, D
IGeneral-Purpose Output IE
IGeneral-Purpose Output IIE
JGeneral-Purpose Input IE
JGeneral-Purpose Input IIE
JGeneral-Purpose Input IIIE
KINT1 outputEE
LINT2 outputEE
MSecondary I2S BCLK inputEE
NSecondary I2S WCLK inputEE
OSecondary I2S DINEE
PSecondary I2S BCLK OUTEE
QSecondary I2S WCLK OUTEE
RSecondary I2S DOUTE
SAux Clock OutputEE
E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)
S(1): The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.
S(2): The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.
S(3): The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.
D: Default Function