JAJSDI7E データシート

JAJSDI7E july 2017 – july 2023 TAS2505-Q1

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGE|24
- MPQF124G

サーマルパッド・メカニカル・データ

RGE|24
- QFND582

発注情報

8.4.3 Multifunction Pins

Table 8-1 shows the possible allocation of pins for specific functions. The PLL input, for example, can be programmed to be any of 4 pins (MCLK, BCLK, DIN, GPIO).

Table 8-1 Multifunction Pin Assignments

		1	2	3	4	5	6	7
	PIN FUNCTION	MCLK	BCLK	WCLK	DIN	GPIO /DOUT	SCLK	MISO
A	PLL Input	S⁽²⁾	S⁽³⁾		E		S⁽⁴⁾
B	Codec Clock Input	S⁽²⁾,D⁽⁵⁾	S⁽³⁾				S⁽⁴⁾
C	I²S BCLK input		S⁽³⁾,D
D	I²S BCLK output		E⁽¹⁾
E	I²S WCLK input			E, D
F	I²S WCLK output			E
G	I²S DIN				E, D
I	General-Purpose Output I					E
I	General-Purpose Output II							E
J	General-Purpose Input I				E
J	General-Purpose Input II					E
J	General-Purpose Input III						E
K	INT1 output					E		E
L	INT2 output					E		E
M	Secondary I²S BCLK input					E	E
N	Secondary I²S WCLK input					E	E
O	Secondary I²S DIN					E	E
P	Secondary I²S BCLK OUT					E		E
Q	Secondary I²S WCLK OUT					E		E
R	Secondary I²S DOUT							E
S	Aux Clock Output					E		E

(1) E: The pin is exclusively used for this function, no other function can be implemented with the same pin. (If GPIO/DOUT has been allocated for General Purpose Output, it cannot be used as the INT1 output at the same time.)

(2) S⁽¹⁾: The MCLK pin can drive the PLL and Codec Clock inputs simultaneously.

(3) S⁽²⁾: The BCLK pin can drive the PLL and Codec Clock and audio interface bit clock inputs simultaneously.

(4) S⁽³⁾: The GPIO/DOUT pin can drive the PLL and Codec Clock inputs simultaneously.

(5) D: Default Function