JAJSN80E August 2009 – May 2022 TCA9535
In the event of a glitch or data corruption, TCA9535 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
Table 9-1 specifies the performance of the power-on reset feature for TCA9535 for both types of power-on reset.
|VCC_FT||Fall rate||See Figure 9-1||0.1||ms|
|VCC_RT||Rise rate||See Figure 9-1||0.01||ms|
|VCC_TRR||Time to re-ramp (when VCC drops to VVOR_MIN – 50 mV or when VCC drops to GND)||See Figure 9-1||1||µs|
|VCC_GH||The level (referenced to VCC) that VCC can glitch down to, but not cause a functional disruption when VCC_GW||See Figure 9-3||1.2||V|
The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated)
|See Figure 9-3||1.5||V|
|VCC_GW||Glitch width that will not cause a functional disruption||See Figure 9-3||10||μs|
|VPORF||Voltage trip point of POR on falling VCC||0.75||1||1||V|
|VPORR||Voltage trip point of POR on rising VCC||1.2||1.5||V|
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-3 and Table 9-1 provide more information on how to measure these specifications.
VPORR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 9-4 and Table 9-1 provide more details on this specification.