JAJSM91 February   2022 TCA9537

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 I2C Bus Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 Interrupt (INT) Output
      3. 8.3.3 RESET Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 Writes
        2. 8.5.1.2 Reads
      2. 8.5.2 Software Reset Call
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Power-On Reset

In the event of a glitch or data corruption, the TCA9537 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in and Figure 10-1.

GUID-CFB5FD73-C7C0-4C7A-A125-55BEE23002A3-low.gifFigure 10-1 VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 10-1 specifies the performance of the power-on reset feature for the device for both types of power-on reset.

Table 10-1 Recommended Supply Sequencing And Ramp Rates
PARAMETER(1)MINMAXUNIT
VCC_FTFall rateSee Figure 10-11ms
VCC_RTRise rateSee Figure 10-10.1ms
VCC_TRRTime to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND)See Figure 10-12μs
VCC_GHLevel that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 µsSee Figure 10-21.2V
VCC_GWGlitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC (For VCC > 3 V)See Figure 10-210μs
(1) All supply sequencing and ramp rate values are measured at TA = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 10-2 and Table 10-1 provide more information on how to measure these specifications.

GUID-F62AE1AA-9CC6-4A23-B0CF-6130DFE4AE84-low.gifFigure 10-2 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 10-3 and Table 10-1 provide more details on this specification.

GUID-CDE32945-1F9D-47E3-8A5E-8541BF71E3D7-low.gifFigure 10-3 VPOR