JAJSI83G May   2012  – November 2019 TCA9548A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Requirements
    7. 7.7 Reset Timing Requirements
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 RESET Input
      2. 9.4.2 Power-On Reset
    5. 9.5 Programming
      1. 9.5.1 I2C Interface
      2. 9.5.2 Device Address
      3. 9.5.3 Bus Transactions
        1. 9.5.3.1 Writes
        2. 9.5.3.2 Reads
      4. 9.5.4 Control Register
      5. 9.5.5 RESET Input
      6. 9.5.6 Power-On Reset
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-On Reset Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

PW Package
24-Pin TSSOP
Top View
RGE Package
24-Pin VQFN
Top View

Pin Functions

PIN TYPE DESCRIPTION
NAME TSSOP
(PW)		 QFN
(RGE)
A0 1 22 I Address input 0. Connect directly to VCC or ground
A1 2 23 I Address input 1. Connect directly to VCC or ground
A2 21 18 I Address input 2. Connect directly to VCC or ground
GND 12 9 — Ground
RESET 3 24 I Active-low reset input. Connect to VCC or VDPUM(1) through a pull-up resistor, if not used
SD0 4 1 I/O Serial data 0. Connect to VDPU0(1) through a pull-up resistor
SC0 5 2 I/O Serial clock 0. Connect to VDPU0(1) through a pull-up resistor
SD1 6 3 I/O Serial data 1. Connect to VDPU1(1) through a pull-up resistor
SC1 7 4 I/O Serial clock 1. Connect to VDPU1(1) through a pull-up resistor
SD2 8 5 I/O Serial data 2. Connect to VDPU2(1) through a pull-up resistor
SC2 9 6 I/O Serial clock 2. Connect to VDPU2(1) through a pull-up resistor
SD3 10 7 I/O Serial data 3. Connect to VDPU3(1) through a pull-up resistor
SC3 11 8 I/O Serial clock 3. Connect to VDPU3(1) through a pull-up resistor
SD4 13 10 I/O Serial data 4. Connect to VDPU4(1) through a pull-up resistor
SC4 14 11 I/O Serial clock 4. Connect to VDPU4(1) through a pull-up resistor
SD5 15 12 I/O Serial data 5. Connect to VDPU5(1) through a pull-up resistor
SC5 16 13 I/O Serial clock 5. Connect to VDPU5(1) through a pull-up resistor
SD6 17 14 I/O Serial data 6. Connect to VDPU6(1) through a pull-up resistor
SC6 18 15 I/O Serial clock 6. Connect to VDPU6(1) through a pull-up resistor
SD7 19 16 I/O Serial data 7. Connect to VDPU7(1) through a pull-up resistor
SC7 20 17 I/O Serial clock 7. Connect to VDPU7(1) through a pull-up resistor
SCL 22 19 I/O Serial clock bus. Connect to VDPUM(1) through a pull-up resistor
SDA 23 20 I/O Serial data bus. Connect to VDPUM(1) through a pull-up resistor
VCC 24 21 Power Supply voltage
(1) VDPUX is the pull-up reference voltage for the associated data line. VDPUM is the master I2C reference voltage and VDPU0-VDPU7 are the slave channel reference voltages.