SLDS145C October   2001  – December 2014 TFP410


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 7.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 7.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Universal Graphics Controller Interface Modes
      2. 7.4.2 Data De-skew Feature
      3. 7.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 7.4.4 Device Configuration and I2C RESET Description
      5. 7.4.5 DE Generator
    5. 7.5 Programming
      1. 7.5.1 I2C interface
    6. 7.6 Register Maps
      1. 7.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 7.6.2  DEV_ID Register (Sub-Address = 03-02) [reset = 0x0410]
      3. 7.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 7.6.4  Reserved Register (Sub-Address = 07-05) [reset = 0x641400]
      5. 7.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xFE]
      6. 7.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 7.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 7.6.8  CFG Register (Sub-Address = 0B)
      9. 7.6.9  RESERVED Register (Sub-Address = 0E-0C) [reset = 0x97D0A9]
      10. 7.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 7.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 7.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 7.6.13 DE_CNT Register (Sub-Address = 37-36) [reset = 0x0000]
      14. 7.6.14 DE_LIN Register (Sub-Address = 39-38) [reset = 0x0000]
      15. 7.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 7.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Data and Control Signals
        2. Configuration Options
        3. Power Supplies Decoupling
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 DVDD
    2. 9.2 TVDD
    3. 9.3 PVDD
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layer Stack
      2. 10.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      3. 10.1.3 DVI Connector
    2. 10.2 Layout Example
    3. 10.3 TI PowerPAD 64-Pin HTQFP Package
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



10 Layout

10.1 Layout Guidelines

10.1.1 Layer Stack

The pinout of Texas Instruments' High Speed Interface (HSI) devices features differential signal pairs and the remaining signals comprise the supply rails, VCC and ground, and lower-speed signals, such as control pins. As an example, consider a device X which is a repeater/re-driver, so both inputs and outputs are high-speed differential signals. These guidelines can be applied to other high-speed devices such as drivers, receivers, multiplexers, and so on.

A minimum of four layers is required to accomplish a low-EMI PCB design. Layer stacking should be in the following order (top-to-bottom): high-speed differential signal layer, ground plane, power plane and control signal layer.

lo_1_slds145.pngFigure 36. PCB Stack Up

10.1.2 Routing High-Speed Differential Signal Traces
(RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)

Trace impedance should be controlled for optimal performance. Each differential pair should be equal in length and symmetrical and should have equal impedance to ground with a trace separation of 2 times to 4 times the height. A differential trace separation of 4 times the height yields about 6% cross-talk (6% effect on impedance).

We recommend that differential trace routing should be side-by-side, though it is not important that the differential traces be tightly coupled together, because tight coupling is not achievable on PCB traces. Typical ratios on PCBs are only 20% to 50%; 99.9% is the value of a well balanced twisted pair cable. Each differential trace should be as short as possible (< 2 inches is preferable) with no 90° angles. These high-speed transmission traces should be on layer 1, which is the top layer.

RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+ signals all route directly from the DVI connector pins to the device, no external components are needed.

10.1.3 DVI Connector

Clear-out holes for connector pins should leave space between pins to allow continuous ground through the pin field. Allow enough spacing in ground plane around signal pins vias however, keep enough copper between vias to allow for ground current to flow between the vias. Avoid creating a large ground plane slot around the entire connector, because minimizing the via capacitance is the goal.

10.2 Layout Example

DVI connector trace matching is shown in Figure 37.

DVIconn.pngFigure 37. DVI Signal Routing

Keep the data lines as far as possible from each other as shown in Figure 38.

dataroute.pngFigure 38. Data Signal Routing

Connect the thermal pad to ground as shown in Figure 39.

gndroute.pngFigure 39. Ground Routing

10.3 TI PowerPAD 64-Pin HTQFP Package

The TFP410 is available in TI’s thermally enhanced 64-pin TQFP PowerPAD package. The PowerPAD package is a 10-mm × 10-mm × 1.0-mm TQFP outline with 0,5 mm lead-pitch. The PowerPAD package has a specially designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline. The TI 64-pin TQFP PowerPAD package offers a backside solder plane that connects directly to the die mount pad for enhanced thermal conduction. For thermal considerations, soldering the backside of the TFP410 to the application board is not required because the device power dissipation is well within the package capability when not soldered.

Soldering the backside of the device to the PCB ground plane is recommended for electrical considerations. Because the die pad is electrically connected to the chip substrate and hence chip ground, connecting the back side of the PowerPAD package to a PCG ground plane provides a low-inductance, low-impedance connection to help improve EMI, ground bounce, and power supply noise performance.

Table 20 contains the thermal properties of the TI 64-pin TQFP PowerPAD package. The 64-pin TQFP non-PowerPAD package is included only for reference.

Table 20. TI 64-Pin TQFP (10-mm × 10-mm × 1.0-mm) / 0.5-mm Lead-Pitch

RθJA Thermal resistance, junction-to-ambient(1)(2) 75.83°C/W 42.20°C/W 21.47°C/W
RθJC Thermal resistance, junction-to-case (1)(2) 7.80°/W 0.38°C/W 0.38°C/W
PD Power handling capabilities of package (1)(2)(3) 0.92 W 1.66 W 3.26 W
(1) Specified with the PowerPAD bond pad on the backside of the package soldered to a 2-oz. Cu plate PCB thermal plane.
(2) Airflow is at 0 LFM (no airflow)
(3) Specified at 150°C junction temperature and 80°C ambient temperature.