JAJSIB3D August   2017  – February 2021 THS4561

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V
    6. 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Mode
      2. 9.4.2 Single-Ended Source to Differential Output Mode
        1. 9.4.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. 9.4.2.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      3. 9.4.3 Differential Input to a Differential Output Mode
        1. 9.4.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Differential Open-Loop Gain and Output Impedance
      2. 10.1.2 Setting Resistor Values Versus Gain
      3. 10.1.3 Noise Analysis
      4. 10.1.4 Factors Influencing Harmonic Distortion
      5. 10.1.5 Input Overdrive Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1.1 Differential Open-Loop Gain and Output Impedance

The most important elements to the closed-loop performance are the open-loop gain and open-loop output impedance. Figure 10-1 shows the simulated differential open-loop gain and phase from the differential inputs to the differential outputs with no load and with a 100-Ω load. Operating with no load removes any effect introduced by the open-loop output impedance to a finite load. Figure 10-2 shows the simulated differential open-loop output impedance.

GUID-F024FF18-D285-4938-B008-F093681F48B8-low.gifFigure 10-1 No-Load and 100-Ω Loaded AOL Gain and Phase
GUID-DE26BCB2-A4AF-494E-9343-BCCDA235B58C-low.gifFigure 10-2 Differential Open-Loop Output Impedance

This open-loop output impedance combines with the load to shift the apparent open-loop gain and phase to the output pins when the load changes. The rail-to-rail output stage shows a very high impedance at low frequencies that reduces with frequency to a lower midrange value and then peaks again at higher frequencies. The maximum value at low frequencies is set by the common-mode sensing resistors to be a 6-kΩ dc value (see Section 9.2.) This high impedance at a low frequency is significantly reduced in closed-loop operation by the loop gain, as shown in the closed-loop output impedance of Figure 7-43. Figure 10-1 compares the no load AOL gain to the AOL gain driving a 100-Ω load that shows the effect of the output impedance. The heavier loads pull the AOL gain down faster to lower crossovers with more phase shift at the lower frequencies.

The much faster phase rolloff for the 100-Ω differential load explains the greater peaked response illustrated in Figure 7-4 and Figure 7-18 when the load decreases. This same effect happens for the RC loads common with converter interface designs. Use the TINA-TI™ model to verify loop phase margin in any design.