JAJSIB3D August 2017 – February 2021 THS4561
In some cases, a characteristic curve can only be generated through simulation. A good example of this scenario is the output balance plot of Figure 7-51. This plot shows the best-case output balance (output differential signal versus output common-mode signal) using exact matching of the external resistors in simulation using a single-ended input to differential output configuration. The actual output balance is set by resistor mismatch at low frequencies but intersects and follows the high-frequency portion of Figure 7-51 at higher frequencies.
The remaining simulated plots include: