JAJSIB3D August   2017  – February 2021 THS4561


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V
    6. 7.6 Typical Characteristics: (VS+) – (VS–) = 12 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range
  8. Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Mode
      2. 9.4.2 Single-Ended Source to Differential Output Mode
        1. AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      3. 9.4.3 Differential Input to a Differential Output Mode
        1. AC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Differential Open-Loop Gain and Output Impedance
      2. 10.1.2 Setting Resistor Values Versus Gain
      3. 10.1.3 Noise Analysis
      4. 10.1.4 Factors Influencing Harmonic Distortion
      5. 10.1.5 Input Overdrive Performance
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 ドキュメントの更新通知を受け取る方法
    2. 13.2 サポート・リソース
    3. 13.3 Trademarks
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 用語集
  14. 14Mechanical, Packaging, and Orderable Information



Setting Resistor Values Versus Gain

The THS4561 offers considerable flexibility in the configuration and selection of resistor values. The design starts with the selection of the feedback resistor value. The 1.5-kΩ feedback resistor value used for the characterization curves is a good compromise between power, noise, and phase margin considerations. With the feedback resistor values selected (and set equal on each side) the input resistors are set to obtain the desired gain with input impedance also set with these input resistors. Differential I/O designs provide an input impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a more complicated input impedance. Most characteristic curves implement the single-ended to differential design as the more challenging requirement over differential-to-differential I/O.

For single-ended, matched, input impedance designs, Table 10-1 illustrates the suggested standard resistors set to approximately a 1.5-kΩ feedback. This table assumes a 50-Ω source and a 50-Ω input match and uses a single resistor on the non-signal input side for gain matching. Better matching is possible using the same three resistors on the non-signal input side as on the input side. Figure 10-3 shows the element values and naming convention for the gain of 1-V/V configuration where the gain is defined from the matched input at RT to the differential output.

GUID-CF0390A5-8ACA-4994-88E2-F017E511E2E1-low.gif Figure 10-3 Single-Ended to Differential Gain of 1 V/V with Input Matching Using Standard Resistor Values

Starting from a target feedback resistor value, the desired input matching impedance, and the target gain (AV), the required input RT value is given by solving the quadratic of Equation 1.

Equation 1. GUID-F40E91D8-D032-4C10-A700-064A4EC756DE-low.gif

When this value is derived, the required input side gain resistor is given by Equation 2 and then the single value for RG2 on the non-signal input side is given by Equation 3:

Equation 2. GUID-6CC3FEB8-658A-4332-9302-9628B761D8F4-low.gif
Equation 3. GUID-44A81603-44A0-4B8F-ADC9-BD0AAADE7688-low.gif

Using these expressions to generate a swept gain table of values results in Table 10-1, where the best standard 1% resistor values are shown to minimize input impedance and gain error to target.

Table 10-1 Swept Gain 50-Ω Input Match with RF = 1.5-kΩ (±1 Standard Values)
0.1 1500 15000 49.9 15000 49.74 0.09973
1 1500 1500 51.1 1500 49.82 0.994
2 1500 750 52.3 768 49.98 1.978
5 1500 287 54.9 316 49.6 5.014
10 1500 137 61.9 165 50.4 10.08

Where an input impedance match is not required, simply set the input resistor to obtain the desired gain without an additional resistor to ground (remove RT in Figure 10-3). This scenario is common when coming from the output of another single-ended op amp (such as the OPA810 or OPA192). This single-ended to differential stage shows a higher input impedance than the physical RG as given by the expression for ZA (active input impedance) shown as Equation 4.

Equation 4. GUID-EE938464-AF0B-4467-BFBD-480225CB713D-low.gif

Using Equation 4 for the gain of 1 V/V with all resistors equal to 1.5-kΩ shows an input impedance of 2 kΩ. The increased input impedance comes from the common-mode input voltage at the amplifier pins moving in the same direction as the input signal. The common-mode input voltage must move to create the current in the non-signal input RG resistor to produce the inverted output. The current flow into the signal-side input resistor is impeded because the common-mode input voltage moves with the input signal, thus increasing the apparent input impedance in the signal input path.