JAJSM25A May   2021  – November 2021 THVD1406 , THVD1426

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings - IEC Specifications
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics (THVD1406)
    9. 6.9  Switching Characteristics (THVD1426)
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • D|8
  • DRL|8
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

Robust and reliable bus node design often requires the use of external transient protection devices in order to protect against surge transients that may occur in industrial environments. Since these transients have a wide frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be applied during PCB design.

  1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across the board.
  2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the path of least impedance and not the path of least resistance.
  3. Design the protection components into the direction of the signal path. Do not force the transient currents to divert from the signal path to reach the protection device.
  4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART and/or controller ICs on the board.
  5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to minimize effective via inductance.
  6. Use 1-kΩ to 10-kΩ pull-up resistors for RE and SHDN lines to connect them together to VCC to reduce the number of GPIO lines to MCU or the number of isolation channels.
  7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.
  8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to less than 1 mA.