JAJSM25A May   2021  – November 2021 THVD1406 , THVD1426

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings - IEC Specifications
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Power Dissipation Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Switching Characteristics (THVD1406)
    9. 6.9  Switching Characteristics (THVD1426)
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Data Rate and Bus Length
        2. 9.2.1.2 Stub Length
        3. 9.2.1.3 Bus Loading
        4. 9.2.1.4 Receiver Failsafe
        5. 9.2.1.5 Transient Protection
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
  • DRL|8
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
│VOD│ Driver differential-output voltage magnitude RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V See Figure 7-1  1.5 2 V
RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V, 4.5 V ≤ Vcc ≤ 5.5 V 2.1 3
RL = 100 Ω, CL = 50 pF See Figure 7-2   2 2.5
RL = 54 Ω, CL = 50 pF 1.5 2
RL = 54 Ω, 4.5 V ≤ Vcc ≤ 5.5 V 2.1 3
Δ│VOD│ Change in magnitude of driver differential-output voltage RL = 54 Ω or 100 Ω, CL = 50 pF See Figure 7-2  –50 50 mV
VOC(SS) Steady-state common-mode output voltage 1 VCC / 2 3 V
ΔVOC Change in differential driver common-mode output voltage –50 50 mV
VOC(PP) Peak-to-peak driver common-mode output voltage RL = 54 Ω or 100 Ω, CL = 50 pF, VCC = 3.3 V  See Figure 7-2  200 mV
│IOS│ Driver short-circuit output current  -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B pin -250 250 mA
Receiver
II Bus input current (driver disabled)  VCC = 0 V or 5.5 V VI = 12 V 75 100 µA
VI = –7 V –97 –70
VIT+ Positive-going receiver differential-input voltage threshold -7 V ≤ VCM ≤ 12 V –70 –45 mV
VIT– Negative-going receiver differential-input voltage threshold –200 –150 mV
VHYS(1) Receiver differential-input voltage threshold hysteresis (VIT+ – VIT– ) 30 50 mV
VOH Receiver high-level output voltage IOH = –4 mA VCC – 0.4 VCC – 0.2 V
VOL Receiver low-level output voltage IOL = 4 mA 0.2 0.4 V
IOZ Receiver high-impedance output current VO = 0 V or VCC, RE = VCC –1 1 µA
Logic
IIN Input current (D, SHDN, RE) –5 5 µA
Supply
ICC Supply current (quiescent) VCC = 3.6 V Driver and receiver enabled SHDN = VCC, RE = 0
D  = 0, no load		 1500 1800 µA
Driver enabled, receiver disabled SHDN = VCC, RE = VCC, D=0, no load 1000 1500 µA
Driver and receiver disabled SHDN = 0, no load 2 4.1 µA
ICC Supply current (quiescent) VCC = 5.5 V Driver and receiver enabled SHDN = VCC, RE = 0
D  = 0, no load		 1700 3000 µA
Driver enabled, receiver disabled SHDN = VCC, RE = VCC, D=0, no load 1300 2500 µA
Driver and receiver disabled SHDN = 0, no load 3 6.9 µA
(1) Under any specific conditions, VIT+ isspecified to be at least VHYS higher thanVIT–.