JAJSDS2A September   2017  – February 2022 TIC10024-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Enable Selection
        3. 8.3.8.3 Thresholds Adjustment
        4. 8.3.8.4 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable / Disable And Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check And Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
  9. Programming
    1. 9.1 SPI Communication Interface Buses
      1. 9.1.1 Chip Select ( CS)
      2. 9.1.2 System Clock (SCLK)
      3. 9.1.3 Slave In (SI)
      4. 9.1.4 Slave Out (SO)
    2. 9.2 SPI Sequence
      1. 9.2.1 Read Operation
      2. 9.2.2 Write Operation
      3. 9.2.3 Status Flag
    3. 9.3 Programming Guidelines
    4. 9.4 Register Maps
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Digital Switch Detection in Automotive Body Control Module
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Systems Examples
      1. 10.3.1 Using TIC10024-Q1 in a 12 V Automotive System
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Register Maps

Table 9-3 lists the memory-mapped registers for the TIC10024-Q1. All register offset addresses not listed in Table 9-3 should be considered as reserved locations and the register contents should not be modified.

Table 9-3 TIC10024-Q1 Registers
OFFSETTYPERESETACRONYMREGISTER NAMESECTION
1hR120hDEVICE_IDDevice ID RegisterGo
2hRC1hINT_STATInterrupt Status RegisterGo
3hRFFFFhCRCCRC Result RegisterGo
4hR0hIN_STAT_MISCMiscellaneous Status RegisterGo
5hR0hIN_STAT_COMPComparator Status RegisterGo
6h-19hRESERVEDRESERVED
1AhR/W0hCONFIGDevice Global Configuration RegisterGo
1BhR/W0hIN_ENInput Enable RegisterGo
1ChR/W0hCS_SELECTCurrent Source/Sink Selection RegisterGo
1Dh-1EhR/W0hWC_CFG0, WC_CFG1Wetting Current Configuration RegisterGo
1Fh-20hR/W0hCCP_CFG0, CCP_CFG1Clean Current Polling RegisterGo
21hR/W0hTHRES_COMPComparator Threshold Control RegisterGo
22h-23hR/W0hINT_EN_COMP1, INT_EN_COMP2Comparator Input Interrupt Generation Control RegisterGo
24hR/W0hINT_EN_CFG0Global Interrupt Generation Control RegisterGo
25h-32hRESERVEDRESERVED

9.4.1 DEVICE_ID register (Offset = 1h) [reset = 20h]

DEVICE_ID is shown in Figure 9-3 and described in Table 9-4.

Return to Summary Table.

This register represents the device ID of the TIC10024-Q1.

Figure 9-3 DEVICE_ID Register
232221201918171615141312
RESERVED
R-0h
11109876543210
RESERVEDMAJORMINOR
R-0hR-12hR-0h
LEGEND: R = Read only
Table 9-4 DEVICE_ID Register Field Descriptions
BitFieldTypeResetDescription
23-11RESERVEDR0h

RESERVED

10-4MAJORR12h

These 7 bits represents major revision ID. For TIC10024-Q1 the major revision ID is 12h.

3-0MINORR0h

These 4 bits represents minor revision ID. For TIC10024-Q1 the minor revision ID is 0h.

9.4.2 INT_STAT Register (Offset = 2h) [reset = 1h]

INT_STAT is shown in Figure 9-4 and described in Table 9-5.

Return to Summary Table.

This register records the information of the event as it occurs in the device. A READ command executed on this register clears its content and resets the register to its default value. The INT pin is released at the rising edge of the CS pin from the READ command.

Figure 9-4 INT_STAT Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCHK_FAILRESERVEDCRC_CALC
R-0hRC-0hR-0hRC-0h
76543210
UVOVTWTSDSSCPRTY_FAILSPI_FAILPOR
RC-0hRC-0hRC-0hRC-0hRC-0hRC-0hRC-0hRC-1h
LEGEND: R = Read only; RC = Read to clear
Table 9-5 INT_STAT Register Field Descriptions
BitFieldTypeResetDescription
23-14RESERVEDR0h

RESERVED

13CHK_FAILRC0h

0h = Default factory setting is successfully loaded upon device initialization or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = An error is detected when loading factory settings into the device upon device initialization.

During device initialization, factory settings are programmed into the device to allow proper device operation. The device performs a self-check after the device is programmed to diagnose whether correct settings are loaded. If the self-check returns an error, the CHK_FAIL bit is flagged to logic 1 along with the POR bit. The host controller is then recommended to initiate a software reset (see section Software Reset) to re-initialize the device and allow correct settings to be re-programmed.

12-9RESERVEDR0hRESERVED
8CRC_CALCRC0h

0h = CRC calculation is running, not started, or was acknowledged after a READ command was executed on the INT_STAT register.

1h = CRC calculation is finished.

CRC calculation (see section Cyclic Redundancy Check (CRC)) can be triggered to make sure correct register values are programmed into the device. Once the calculation is completed, the CRC_CALC bit is flagged to logic 1 to indicate completion of the calculation, and the result can then be accessed from the CRC (offset = 3h) register.

7UVRC0h

0h = No under-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Under-voltage condition occurred or cleared on the VS pin.

When the UV bit is flagged to logic 1, it indicates the Under-Voltage (UV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the UV operation, please refer to section VS under-voltage (UV) condition.

6OVRC0h

0h = No over-voltage condition occurred or cleared on the VS pin, or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Over-voltage condition occurred or cleared on the VS pin.

When the OV bit is flagged to logic 1, it indicates the Over-Voltage (OV) event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the OV operation, please refer to section VS over-voltage (OV) condition.

5TWRC0h

0h = No temperature warning event occurred or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Temperature warning event occurred or cleared.

When the TW bit is flagged to logic 1, it indicates the temperature warning event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature warning operation, please refer to section Temperature Warning (TW)

4TSDRC0h

0h = No temperature Shutdown event occurred or the event status got cleared after a READ command was executed on the INT_STAT register.

1h = Temperature Shutdown event occurred or cleared.

When the TSD bit is flagged to logic 1, it indicates the temperature shutdown event has occurred. The bit is also flagged to logic 1 when the event clears. For more details about the temperature shutdown operation, please refer to section Temperature shutdown (TSD)

3SSCRC0h

0h = No switch state change occurred or the status got cleared after a READ command was executed on the INT_STAT register.

1h = Switch state change occurred.

The Switch State Change (SSC) bit indicates whether input threshold crossing has occurred from switch inputs IN0 to IN23. This bit is also flagged to logic 1 after the first polling cycle is completed after device polling is triggered.

2PRTY_FAILRC0h

0h = No parity error occurred in the last received SI stream or the error status got cleared after a READ command was executed on the INT_STAT register.

1h = Parity error occurred.

When the PRTY_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The value of this register bit is mirrored to the PRTY_FLAG SPI status flag.

1SPI_FAILRC0h

0h = 32 clock pulse during a CS = low sequence was detected or the error status got cleared after a READ command was executed on the INT_STAT register.

1h = SPI error occurred

When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI responder in (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit is flagged to logic 1, and the data received is considered invalid. The value of this register bit is mirrored to the SPI_FLAG SPI status flag. Note the SPI_FAIL bit is not flagged if SCLK is not present.

0PORRC1h

0h = no Power-On-Reset (POR) event occurred or the status got cleared after a READ command was executed on the INT_STAT register.

1h = Power-On-Reset (POR) event occurred.

The Power-On-Reset (POR) interrupt bit indicates whether a reset event has occurred. A reset event sets the registers to their default values and re-initializes the device state machine. This bit is asserted after a successful power-on-reset, hardware reset, or software reset. The value of this register bit is mirrored to the POR SPI status flag.

9.4.3 CRC Register (Offset = 3h) [reset = FFFFh]

CRC is shown in Figure 9-5 and described in Table 9-6.

Return to Summary Table.

This register returns the CRC-16-CCCIT calculation result. The microcontroller can compare this value with its own calculated value to ensure correct register settings are programmed to the device.

Figure 9-5 CRC Register
23222120191817161514131211109876543210
RESERVEDCRC
R-0hR-FFFFh
LEGEND: R = Read only
Table 9-6 CRC Register Field Descriptions
BitFieldTypeResetDescription
23-16RESERVEDR0h

Reserved

15-0CRCRFFFFh

CRC-16-CCITT calculation result: Bit1: LSB of CRC Bit16: MSB or CRC

9.4.4 IN_STAT_MISC Register (Offset = 4h) [reset = 0h]

IN_STAT_MISC is shown in Figure 9-6 and described in Table 9-7.

Return to Summary Table.

This register indicates current device status unrelated to switch input monitoring.

Figure 9-6 IN_STAT_MISC Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDUV_STATOV_STATTW_STATTSD_STAT
R-0hR-0hR-0hR-0hR-0h
Table 9-7 IN_STAT_MISC Register Field Descriptions
BitFieldTypeResetDescription
23-4RESERVEDR0h

Reserved

3UV_STATR0h

0h = VS voltage is above the under-voltage condition threshold.

1h = VS voltage is below the under-voltage condition threshold.

2OV_STATR0h

0h = VS voltage is below the over-voltage condition threshold.

1h = VS voltage is above the over-voltage condition threshold.

1TW_STATR0h

0h = Device junction temperature is below the temperature warning threshold TTW.

1h = Device junction temperature is above the temperature warning threshold TTW.

0TSD_STATR0h

0h = Device junction temperature is below the temperature shutdown threshold TTSD.

1h = Device junction temperature is above the temperature shutdown threshold TTSD.

9.4.5 IN_STAT_COMP Register (Offset = 5h) [reset = 0h]

IN_STAT_COMP is shown in Figure 9-7 and described in Table 9-8.

Return to Summary Table.

This register indicates whether an input is below or above the comparator threshold.

Figure 9-7 IN_STAT_COMP Register
2322212019181716
INC_23INC_22INC_21INC_20INC_19INC_18INC_17INC_16
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
INC_15INC_14INC_13INC_12INC_11INC_10INC_9INC_8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
INC_7INC_6INC_5INC_4INC_3INC_2INC_1INC_0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R = Read only
Table 9-8 IN_STAT_COMP Register Field Descriptions
BitFieldTypeResetDescription
23INC_23R0h

0h = Input IN23 is below the comparator threshold.

1h = Input IN23 is above the comparator threshold.

22INC_22R0h

0h = Input IN22 is below the comparator threshold.

1h = Input IN22 is above the comparator threshold.

21INC_21R0h

0h = Input IN21 is below the comparator threshold.

1h = Input IN21 is above the comparator threshold.

20INC_20R0h

0h = Input IN20 is below the comparator threshold.

1h = Input IN20 is above the comparator threshold.

19INC_19R0h

0h = Input IN19 is below the comparator threshold.

1h = Input IN19 is above the comparator threshold.

18INC_18R0h

0h = Input IN18 is below the comparator threshold.

1h = Input IN18 is above the comparator threshold.

17INC_17R0h

0h = Input IN17 is below the comparator threshold.

1h = Input IN17 is above the comparator threshold.

16INC_16R0h

0h = Input IN16 is below the comparator threshold.

1h = Input IN16 is above the comparator threshold.

15INC_15R0h

0h = Input IN15 is below the comparator threshold.

1h = Input IN15 is above the comparator threshold.

14INC_14R0h

0h = Input IN14 is below the comparator threshold.

1h = Input IN14 is above the comparator threshold.

13INC_13R0h

0h = Input IN13 is below the comparator threshold.

1h = Input IN13 is above the comparator threshold.

12INC_12R0h

0h = Input IN12 is below the comparator threshold.

1h = Input IN12 is above the comparator threshold.

11INC_11R0h

0h = Input IN11 is below the comparator threshold.

1h = Input IN11 is above the comparator threshold.

10INC_10R0h

0h = Input IN10 is below the comparator threshold.

1h = Input IN10 is above the comparator threshold.

9INC_9R0h

0h = Input IN9 is below the comparator threshold.

1h = Input IN9 is above the comparator threshold.

8INC_8R0h

0h = Input IN8 is below the comparator threshold.

1h = Input IN8 is above the comparator threshold.

7INC_7R0h

0h = Input IN7 is below the comparator threshold.

1h = Input IN7 is above the comparator threshold.

6INC_6R0h

0h = Input IN6 is below the comparator threshold.

1h = Input IN6 is above the comparator threshold.

5INC_5R0h

0h = Input IN5 is below the comparator threshold.

1h = Input IN5 is above the comparator threshold.

4INC_4R0h

0h = Input IN4 is below the comparator threshold.

1h = Input IN4 is above the comparator threshold.

3INC_3R0h

0h = Input IN3 is below the comparator threshold.

1h = Input IN3 is above the comparator threshold.

2INC_2R0h

0h = Input IN2 is below the comparator threshold.

1h = Input IN2 is above the comparator threshold.

1INC_1R0h

0h = Input IN1 is below the comparator threshold.

1h = Input IN1 is above the comparator threshold.

0INC_0R0h

0h = Input IN0 is below the comparator threshold.

1h = Input IN0 is above the comparator threshold.

9.4.6 CONFIG Register (Offset = 1Ah) [reset = 0h]

CONFIG is shown in Figure 9-8 and described in Table 9-9.

Return to Summary Table.

Figure 9-8 CONFIG Register
2322212019181716
RESERVEDTW_CUR_DIS_CSI
R-0hR/W-0h
15141312111098
DET_FILTERTW_CUR_DIS_CSOINT_CONFIGTRIGGERPOLL_ENCRC_TPOLL_ACT_TIME
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
POLL_ACT_TIMEPOLL_TIMERESET
R/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 9-9 CONFIG Register Field Descriptions
BitFieldTypeResetDescription
23-17RESERVEDR0h

Reserved

16TW_CUR_DIS_CSIR/W0h

0h = Enable wetting current reduction (to 2 mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSI.

1h = Disable wetting current reduction (to 2 mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSI.

15-14DET_FILTERR/W0h

For detailed descriptions for the detection filter, refer to section Detection Filter.

0h = every sample is valid and taken for threshold evaluation

1h = 2 consecutive and equal samples required to be valid data

2h = 3 consecutive and equal samples required to be valid data

3h = 4 consecutive and equal samples required to be valid data

13TW_CUR_DIS_CSOR/W0h

0h = Enable wetting current reduction (to 2mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSO.

1h = Disable wetting current reduction (to 2mA) for 10mA and 15mA settings upon TW event for all inputs enabled with CSO.

12INT_CONFIGR/W0h

For detailed descriptions for the INT pin assertion scheme, refer to section Interrupt Generation and /INT Assertion.

0h = INT pin assertion scheme set to static

1h = INT pin assertion scheme set to dynamic

11TRIGGERR/W0h

When the TRIGGER bit is set to logic 1, normal device operation (wetting current activation and polling) starts. To stop device operation and keep the device in an idle state, de-assert this bit to 0. After device normal operation is triggered, if at any time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER to logic 0 to stop device operation. Once the re-configuration is completed, the microcontroller can set the TRIGGER bit back to logic 1 to re-start device operation. If re-configuration is done on the fly without first stopping the device operation, false switch status could be reported and accidental interrupt might be issued. The following register bits are the exception and can be configured when TRIGGER bit is set to logic 1:

– TRIGGER (bit 11 of the CONFIG register)

– CRC_T (bit 9 of the CONFIG register)

– RESET (bit 0 of the CONFIG register)

– The CCP_CFG1 register

0h = Stop TIC10024-Q1 from normal operation.

1h = Trigger TIC10024-Q1 normal operation

10POLL_ENR/W0h

0h = Polling disabled. Device operates in continuous mode.

1h = Polling enabled and the device operates in one of the polling modes.

9CRC_TR/W0h

Set this bit to 1 to trigger a CRC calculation on all the configuration register bits. Once triggered, it is strongly recommended the SPI commander does not change the content of the configuration registers until the CRC calculation is completed to avoid erroneous CRC calculation result. The TIC10024-Q1 sets the CRC_CALC interrupt bit and asserts the INT pin low when the CRC calculation is completed. The calculated result will be available in the CRC register. This bit self-clears back to 0 after CRC calculation is executed.

0h = no CRC calculation triggered

1h = trigger CRC calculation

8-5POLL_ACT_TIMER/W0h

0h = 64μs

1h = 128μs

2h = 192μs

3h = 256μs

4h = 320μs

5h = 384μs

6h = 448μs

7h = 512μs

8h = 640μs

9h = 768μs

Ah = 896μs

Bh = 1024μs

Ch = 2048μs

Dh-15h = 512μs (most frequently-used setting)

4-1POLL_TIMER/W0h

0h = 2ms

1h = 4ms

2h = 8ms

3h = 16ms

4h = 32ms

5h = 48ms

6h = 64ms

7h = 128ms

8h = 256ms

9h = 512ms

Ah = 1024ms

Bh = 2048ms

Ch = 4096ms

Dh-15h = 8ms (most frequently-used setting)

0RESETR/W0h

0h = No reset

1h = Trigger software reset of the device.

9.4.7 IN_EN Register (Offset = 1Bh) [reset = 0h]

IN_EN is shown in Figure 9-9 and described in Table 9-10.

Return to Summary Table.

Figure 9-9 IN_EN Register
2322212019181716
IN_EN_23IN_EN_22IN_EN_21IN_EN_20IN_EN_19IN_EN_18IN_EN_17IN_EN_16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
IN_EN_15IN_EN_14IN_EN_13IN_EN_12IN_EN_11IN_EN_10IN_EN_9IN_EN_8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
IN_EN_7IN_EN_6IN_EN_5IN_EN_4IN_EN_3IN_EN_2IN_EN_1IN_EN_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 9-10 IN_EN Register Field Descriptions
BitFieldTypeResetDescription
23IN_EN_23R/W0h

0h = Input channel IN23 disabled. Polling sequence skips this channel

1h = Input channel IN23 enabled.

22IN_EN_22R/W0h

0h = Input channel IN22 disabled. Polling sequence skips this channel

1h = Input channel IN22 enabled.

21IN_EN_21R/W0h

0h = Input channel IN21 disabled. Polling sequence skips this channel

1h = Input channel IN21 enabled.

20IN_EN_20R/W0h

0h = Input channel IN20 disabled. Polling sequence skips this channel

1h = Input channel IN20 enabled.

19IN_EN_19R/W0h

0h = Input channel IN19 disabled. Polling sequence skips this channel

1h = Input channel IN19 enabled.

18IN_EN_18R/W0h

0h = Input channel IN18 disabled. Polling sequence skips this channel

1h = Input channel IN18 enabled.

17IN_EN_17R/W0h

0h = Input channel IN17 disabled. Polling sequence skips this channel

1h = Input channel IN17 enabled.

16IN_EN_16R/W0h

0h = Input channel IN16 disabled. Polling sequence skips this channel

1h = Input channel IN16 enabled.

15IN_EN_15R/W0h

0h = Input channel IN15 disabled. Polling sequence skips this channel

1h = Input channel IN15 enabled.

14IN_EN_14R/W0h

0h = Input channel IN14 disabled. Polling sequence skips this channel

1h = Input channel IN14 enabled.

13IN_EN_13R/W0h

0h = Input channel IN13 disabled. Polling sequence skips this channel

1h = Input channel IN13 enabled.

12IN_EN_12R/W0h

0h = Input channel IN12 disabled. Polling sequence skips this channel

1h = Input channel IN12 enabled.

11IN_EN_11R/W0h

0h = Input channel IN11 disabled. Polling sequence skips this channel

1h = Input channel IN11 enabled.

10IN_EN_10R/W0h

0h = Input channel IN10 disabled. Polling sequence skips this channel

1h = Input channel IN10 enabled.

9IN_EN_9R/W0h

0h = Input channel IN9 disabled. Polling sequence skips this channel

1h = Input channel IN9 enabled.

8IN_EN_8R/W0h

0h = Input channel IN8 disabled. Polling sequence skips this channel

1h = Input channel IN8 enabled.

7IN_EN_7R/W0h

0h = Input channel IN7 disabled. Polling sequence skips this channel

1h = Input channel IN7 enabled.

6IN_EN_6R/W0h

0h = Input channel IN6 disabled. Polling sequence skips this channel

1h = Input channel IN6 enabled.

5IN_EN_5R/W0h

0h = Input channel IN5 disabled. Polling sequence skips this channel

1h = Input channel IN5 enabled.

4IN_EN_4R/W0h

0h = Input channel IN4 disabled. Polling sequence skips this channel

1h = Input channel IN4 enabled.

3IN_EN_3R/W0h

0h = Input channel IN3 disabled. Polling sequence skips this channel

1h = Input channel IN3 enabled.

2IN_EN_2R/W0h

0h = Input channel IN2 disabled. Polling sequence skips this channel

1h = Input channel IN2 enabled.

1IN_EN_1R/W0h

0h = Input channel IN1 disabled. Polling sequence skips this channel

1h = Input channel IN1 enabled.

0IN_EN_0R/W0h

0h = Input channel IN0 disabled. Polling sequence skips this channel

1h = Input channel IN0 enabled.

9.4.8 CS_SELECT Register (Offset = 1Ch) [reset = 0h]

CS_SELECT is shown in Figure 9-10 and described in Table 9-11.

Return to Summary Table.

Figure 9-10 CS_SELECT Register
232221201918171615141312
RESERVED
R-0h
11109876543210
RESERVEDCS_IN9CS_IN8CS_IN7CS_IN6CS_IN5CS_IN4CS_IN3CS_IN2CS_IN1CS_IN0
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 9-11 CS_SELECT Register Field Descriptions
BitFieldTypeResetDescription
23-10RESERVEDR0h

Reserved

9CS_IN9R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

8CS_IN8R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

7CS_IN7R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

6CS_IN6R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

5CS_IN5R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

4CS_IN4R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

3CS_IN3R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

2CS_IN2R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

1CS_IN1R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

0CS_IN0R/W0h

0h = Current Source (CSO) selected

1h = Current Sink (CSI) selected

9.4.9 WC_CFG0 Register (Offset = 1Dh) [reset = 0h]

WC_CFG0 is shown in Figure 9-11 and described in Table 9-12.

Return to Summary Table.

Figure 9-11 WC_CFG0 Register
232221201918171615141312
WC_IN11WC_IN10WC_IN8_IN9WC_IN6_IN7
R/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
WC_IN5WC_IN4WC_IN2_IN3WC_IN0_IN1
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 9-12 WC_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-21WC_IN11R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

20-18WC_IN10R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

17-15WC_IN8_IN9R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

14-12WC_IN6_IN7R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

11-9WC_IN5R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

8-6WC_IN4R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

5-3WC_IN2_IN3R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

2-0WC_IN0_IN1R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

9.4.10 WC_CFG1 Register (Offset = 1Eh) [reset = 0h]

WC_CFG1 is shown in Figure 9-12 and described in Table 9-13.

Return to Summary Table.

Figure 9-12 WC_CFG1 Register
232221201918171615141312
RESERVEDAUTO_SCALE_DIS_CSIAUTO_SCALE_DIS_CSOWC_IN23WC_IN22WC_IN20_IN21
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
WC_IN18_IN19WC_IN16_IN17WC_IN14_IN15WC_IN12_IN13
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 9-13 WC_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
23RESERVEDR0h

Reserved

22AUTO_SCALE_DIS_CSIR/W0h

0h = Enable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSI

1h = Disable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CS

For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling.

21AUTO_SCALE_DIS_CSOR/W0h

0h = Enable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSO

1h = Disable wetting current auto-scaling (to 2mA) in continuous mode for 10mA and 15mA settings upon switch closure for all inputs enabled with CSO

For detailed descriptions for the wetting current auto-scaling, refer to section Wetting Current Auto-Scaling.

20-18WC_IN23R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

17-15WC_IN22R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

14-12WC_IN20_IN21R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

11-9WC_IN18_IN19R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

8-6WC_IN16_IN17R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

5-3WC_IN14_IN15R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

2-0WC_IN12_IN13R/W0h

0h = no wetting current

1h = 1mA (typ.) wetting current

2h = 2mA (typ.) wetting current

3h = 5mA (typ.) wetting current

4h = 10mA (typ.) wetting current

5h-7h = 15mA (typ.) wetting current

9.4.11 CCP_CFG0 Register (Offset = 1Fh) [reset = 0h]

CCP_CFG0 is shown in Figure 9-13 and described in Table 9-14.

Return to Summary Table.

Figure 9-13 CCP_CFG0 Register
232221201918171615141312
RESERVED
R-0h
11109876543210
RESERVEDCCP_TIMEWC_CCP3WC_CCP2WC_CCP1WC_CCP0
R-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only
Table 9-14 CCP_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-7RESERVEDR0h

Reserved

6-4CCP_TIMER/W0h

Wetting current activation time in CCP mode

0h = 64μs

1h = 128μs

2h = 192μs

3h = 256μs

4h = 320μs

5h = 384μs

6h = 448μs

7h = 512μs

3WC_CCP3R/W0h

Wetting current setting for IN18 to IN23 in CCP mode

0h = 10mA (typ.) wetting current

1h = 15mA (typ.) wetting current

2WC_CCP2R/W0h

Wetting current setting for IN12 to IN17 in CCP mode

0h = 10mA (typ.) wetting current

1h = 15mA (typ.) wetting current

1WC_CCP1R/W0h

Wetting current setting for IN6 to IN11 in CCP mode

0h = 10mA (typ.) wetting current

1h = 15mA (typ.) wetting current

0WC_CCP0R/W0h

Wetting current setting for IN0 to IN5 in CCP mode

0h = 10mA (typ.) wetting current

1h = 15mA (typ.) wetting current

9.4.12 CCP_CFG1 Register (Offset = 20h) [reset = 0h]

CCP_CFG1 is shown in Figure 9-14 and described in Table 9-15.

Return to Summary Table.

Figure 9-14 CCP_CFG1 Register
2322212019181716
CCP_IN23CCP_IN22CCP_IN21CCP_IN20CCP_IN19CCP_IN18CCP_IN17CCP_IN16
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CCP_IN15CCP_IN14CCP_IN13CCP_IN12CCP_IN11CCP_IN10CCP_IN9CCP_IN8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CCP_IN7CCP_IN6CCP_IN5CCP_IN4CCP_IN3CCP_IN2CCP_IN1CCP_IN0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 9-15 CCP_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
23CCP_IN23R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

22CCP_IN22R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

21CCP_IN21R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

20CCP_IN20R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

19CCP_IN19R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

18CCP_IN18R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

17CCP_IN17R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

16CCP_IN16R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

15CCP_IN15R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

14CCP_IN14R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

13CCP_IN13R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

12CCP_IN12R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

11CCP_IN11R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

10CCP_IN10R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

9CCP_IN9R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

8CCP_IN8R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

7CCP_IN7R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

6CCP_IN6R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

5CCP_IN5R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

4CCP_IN4R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

3CCP_IN3R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

2CCP_IN2R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

1CCP_IN1R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

0CCP_IN0R/W0h

0h = no CCP wetting current

1h = CCP wetting current activated

9.4.13 THRES_COMP Register (Offset = 21h) [reset = 0h]

THRES_COMP is shown in Figure 9-15 and described in Table 9-16.

Return to Summary Table.

Figure 9-15 THRES_COMP Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDTHRES_COMP_IN20_IN23THRES_COMP_IN16_IN19
R-0hR/W-0hR/W-0h
76543210
THRES_COMP_IN12_IN15THRES_COMP_IN8_IN11THRES_COMP_IN4_IN7THRES_COMP_IN0_IN3
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 9-16 THRES_COMP Register Field Descriptions
BitFieldTypeResetDescription
23-12RESERVEDR0h

Reserved

11-10THRES_COMP_IN20_IN23R/W0h

These 2 bits configures the comparator thresholds for input channels IN20 to IN23

0h = comparator threshold set to 2V

1h = comparator threshold set to 2.7V

2h = comparator threshold set to 3V

3h = comparator threshold set to 4V

9-8THRES_COMP_IN16_IN19R/W0h

These 2 bits configures the comparator thresholds for input channels IN16 to IN19

0h = comparator threshold set to 2V

1h = comparator threshold set to 2.7V

2h = comparator threshold set to 3V

3h = comparator threshold set to 4V

7-6THRES_COMP_IN12_IN15R/W0h

These 2 bits configures the comparator thresholds for input channels IN12 to IN15

0h = comparator threshold set to 2V

1h = comparator threshold set to 2.7V

2h = comparator threshold set to 3V

3h = comparator threshold set to 4V

5-4THRES_COMP_IN8_IN11R/W0h

These 2 bits configures the comparator thresholds for input channels IN8 to IN11

0h = comparator threshold set to 2V

1h = comparator threshold set to 2.7V

2h = comparator threshold set to 3V

3h = comparator threshold set to 4V

3-2THRES_COMP_IN4_IN7R/W0h

These 2 bits configures the comparator thresholds for input channels IN4 to IN7

0h = comparator threshold set to 2V

1h = comparator threshold set to 2.7V

2h = comparator threshold set to 3V

3h = comparator threshold set to 4V

1-0THRES_COMP_IN0_IN3R/W0h

These 2 bits configures the comparator thresholds for input channels IN0 to IN3

0h = comparator threshold set to 2V

1h = comparator threshold set to 2.7V

2h = comparator threshold set to 3V

3h = comparator threshold set to 4V

9.4.14 INT_EN_COMP1 Register (Offset = 22h) [reset = 0h]

INT_EN_COMP1 is shown in Figure 9-16 and described in Table 9-17.

Return to Summary Table.

Figure 9-16 INT_EN_COMP1 Register
232221201918171615141312
INC_EN_11INC_EN_10INC_EN_9INC_EN_8INC_EN_7INC_EN_6
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
INC_EN_5INC_EN_4INC_EN_3INC_EN_2INC_EN_1INC_EN_0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 9-17 INT_EN_COMP1 Register Field Descriptions
BitFieldTypeResetDescription
23-22INC_EN_11R/W0h

0h = no interrupt generation for IN11

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN11

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN11

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN11

21-20INC_EN_10R/W0h

0h = no interrupt generation for IN10

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN10

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN10

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN10

19-18INC_EN_9R/W0h

0h = no interrupt generation for IN9

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN9

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN9

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN9

17-16INC_EN_8R/W0h

0h = no interrupt generation for IN8

1h = interrupt generation on rising edge above THRES_COMP_IN8_IN11 for IN8

2h = interrupt generation on falling edge below THRES_COMP_IN8_IN11 for IN8

3h = interrupt generation on falling and rising edge of THRES_COMP_IN8_IN11 for IN8

15-14INC_EN_7R/W0h

0h = no interrupt generation for IN7

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN7

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN7

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN7

13-12INC_EN_6R/W0h

0h = no interrupt generation for IN6

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN6

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN6

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN6

11-10INC_EN_5R/W0h

0h = no interrupt generation for IN5

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN5

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN5

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN5

9-8INC_EN_4R/W0h

0h = no interrupt generation for IN4

1h = interrupt generation on rising edge above THRES_COMP_IN4_IN7 for IN4

2h = interrupt generation on falling edge below THRES_COMP_IN4_IN7 for IN4

3h = interrupt generation on falling and rising edge of THRES_COMP_IN4_IN7 for IN4

7-6INC_EN_3R/W0h

0h = no interrupt generation for IN3

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN3

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN3

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN3

5-4INC_EN_2R/W0h

0h = no interrupt generation for IN2

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN2

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN2

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN2

3-2INC_EN_1R/W0h

0h = no interrupt generation for IN1

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN1

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN1

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN1

1-0INC_EN_0R/W0h

0h = no interrupt generation for IN0

1h = interrupt generation on rising edge above THRES_COMP_IN0_IN3 for IN0

2h = interrupt generation on falling edge below THRES_COMP_IN0_IN3 for IN0

3h = interrupt generation on falling and rising edge of THRES_COMP_IN0_IN3 for IN0

9.4.15 INT_EN_COMP2 Register (Offset = 23h) [reset = 0h]

INT_EN_COMP2 is shown in Figure 9-17 and described in Table 9-18.

Return to Summary Table.

Figure 9-17 INT_EN_COMP2 Register
232221201918171615141312
INC_EN_23INC_EN_22INC_EN_21INC_EN_20INC_EN_19INC_EN_18
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
11109876543210
INC_EN_17INC_EN_16INC_EN_15INC_EN_14INC_EN_13INC_EN_12
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write
Table 9-18 INT_EN_COMP2 Register Field Descriptions
BitFieldTypeResetDescription
23-22INC_EN_23R/W0h

0h = no interrupt generation for IN23

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN23

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN23

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN23

21-20INC_EN_22R/W0h

0h = no interrupt generation for IN22

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN22

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN22

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN22

19-18INC_EN_21R/W0h

0h = no interrupt generation for IN21

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN21

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN21

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN21

17-16INC_EN_20R/W0h

0h = no interrupt generation for IN20

1h = interrupt generation on rising edge above THRES_COMP_IN20_IN23 for IN20

2h = interrupt generation on falling edge below THRES_COMP_IN20_IN23 for IN20

3h = interrupt generation on falling and rising edge of THRES_COMP_IN20_IN23 for IN20

15-14INC_EN_19R/W0h

0h = no interrupt generation for IN19

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN19

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN19

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN19

13-12INC_EN_18R/W0h

0h = no interrupt generation for IN18

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN18

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN18

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN18

11-10INC_EN_17R/W0h

0h = no interrupt generation for IN17

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN17

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN17

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN17

9-8INC_EN_16R/W0h

0h = no interrupt generation for IN16

1h = interrupt generation on rising edge above THRES_COMP_IN16_IN19 for IN16

2h = interrupt generation on falling edge below THRES_COMP_IN16_IN19 for IN16

3h = interrupt generation on falling and rising edge of THRES_COMP_IN16_IN19 for IN16

7-6INC_EN_15R/W0h

0h = no interrupt generation for IN15

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN15

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN15

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN15

5-4INC_EN_14R/W0h

0h = no interrupt generation for IN14

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN14

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN14

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN14

3-2INC_EN_13R/W0h

0h = no interrupt generation for IN13

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN13

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN13

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN13

1-0INC_EN_12R/W0h

0h = no interrupt generation for IN12

1h = interrupt generation on rising edge above THRES_COMP_IN12_IN15 for IN12

2h = interrupt generation on falling edge below THRES_COMP_IN12_IN15 for IN12

3h = interrupt generation on falling and rising edge of THRES_COMP_IN12_IN15 for IN12

9.4.16 INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]

INT_EN_CFG0 is shown in Figure 9-18 and described in Table 9-19.

Return to Summary Table.

Figure 9-18 INT_EN_CFG0 Register
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
CRC_CALC_ENUV_ENOV_ENTW_ENTSD_ENSSC_ENPRTY_FAIL_ENSPI_FAIL_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only
Table 9-19 INT_EN_CFG0 Register Field Descriptions
BitFieldTypeResetDescription
23-8RESERVEDR0h

Reserved

7CRC_CALC_ENR/W0h

0h = INT pin assertion due to CRC calculation completion disabled.

1h = INT pin assertion due to CRC calculation completion enabled.

6UV_ENR/W0h

0h = INT pin assertion due to UV event disabled.

1h = INT pin assertion due to UV event enabled.

5OV_ENR/W0h

0h = INT pin assertion due to OV event disabled.

1h = INT pin assertion due to OV event enabled.

4TW_ENR/W0h

0h = INT pin assertion due to TW event disabled.

1h = INT pin assertion due to TW event enabled.

3TSD_ENR/W0h

0h = INT pin assertion due to TSD event disabled.

1h = INT pin assertion due to TSD event enabled.

2SSC_ENR/W0h

0h = INT pin assertion due to SSC event disabled.

1h = INT pin assertion due to SSC event enabled.

1PRTY_FAIL_ENR/W0h

0h = INT pin assertion due to parity fail event disabled.

1h = INT pin assertion due to parity fail event enabled.

0SPI_FAIL_ENR/W0h

0h = INT pin assertion due to SPI fail event disabled.

1h = INT pin assertion due to SPI fail event enabled.