7.6.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
OPMODE_CFG is shown in Figure 37 and described in Table 17.
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Figure 37. OPMODE_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
OSC_SEL |
CLK_DIV[3:0] |
R-0b |
R/W-0b |
R/W-0b |
|
Table 17. OPMODE_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-5 |
RESERVED |
R |
0b |
Reserved. Reads return 0b. |
4 |
OSC_SEL |
R/W |
0b |
Selects the oscillator for internal timing generation.
0b = High speed oscillator.
1b = Low power oscillator.
|
3-0 |
CLK_DIV[3:0] |
R/W |
0b |
Sampling speed control. Refer to section on Oscillator and Timing Control for details. |