SLLSEE3D August   2013  – April 2016 TLK105L , TLK106L

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Pin Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Serial Management Interface (SMI)
    3. 3.3 MAC Data Interface
    4. 3.4 10Mbs and 100Mbs PMD Interface
    5. 3.5 Clock Interface
    6. 3.6 LED Interface
    7. 3.7 Reset and Power Down
    8. 3.8 Power and Bias Connections
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 20
      1. 4.4.1 TLK105L 32-Pin Industrial Device (85°C) Thermal Characteristics
    5. 4.5 TLK106L 32-Pin Extended Temperature (105°C) Device Thermal Characteristics
    6. 4.6 DC Characteristics, VDD_IO
    7. 4.7 DC Characteristics
    8. 4.8 Power Supply Characteristics
      1. 4.8.1 Active Power, Single Supply Operation
      2. 4.8.2 Active Power, Dual Supply Operation
      3. 4.8.3 Power-Down Power
    9. 4.9 AC Specifications
      1. 4.9.1  Power Up Timing
      2. 4.9.2  Reset Timing
      3. 4.9.3  MII Serial Management Timing
      4. 4.9.4  100Mb/s MII Transmit Timing
      5. 4.9.5  100Mb/s MII Receive Timing
      6. 4.9.6  100Base-TX Transmit Packet Latency Timing
      7. 4.9.7  100Base-TX Transmit Packet Deassertion Timing
      8. 4.9.8  100Base-TX Transmit Timing (tR/F and Jitter)
      9. 4.9.9  100Base-TX Receive Packet Latency Timing
      10. 4.9.10 100Base-TX Receive Packet Deassertion Timing
      11. 4.9.11 10Mbs MII Transmit Timing
      12. 4.9.12 10Mb/s MII Receive Timing
      13. 4.9.13 10Base-T Transmit Timing (Start of Packet)
      14. 4.9.14 10Base-T Transmit Timing (End of Packet)
      15. 4.9.15 10Base-T Receive Timing (Start of Packet)
      16. 4.9.16 10Base-T Receive Timing (End of Packet)
      17. 4.9.17 10Mb/s Jabber Timing
      18. 4.9.18 10Base-T Normal Link Pulse Timing
      19. 4.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
      20. 4.9.20 100Base-TX Signal Detect Timing
      21. 4.9.21 100Mbs Loopback Timing
      22. 4.9.22 10Mbs Internal Loopback Timing
      23. 4.9.23 RMII Transmit Timing
      24. 4.9.24 RMII Receive Timing
      25. 4.9.25 Isolation Timing
  5. 5Detailed Description
    1. 5.1 Hardware Configuration
      1. 5.1.1  Bootstrap Configuration
      2. 5.1.2  Power Supply Configuration
        1. 5.1.2.1 Single Supply Operation
        2. 5.1.2.2 Dual Supply Operation
        3. 5.1.2.3 Variable IO Voltage
      3. 5.1.3  IO Pins Hi-Z State During Reset
      4. 5.1.4  Auto-Negotiation
      5. 5.1.5  Auto-MDIX
      6. 5.1.6  MII Isolate Mode
      7. 5.1.7  PHY Address
      8. 5.1.8  LED Interface
      9. 5.1.9  Loopback Functionality
        1. 5.1.9.1 Near-End Loopback
        2. 5.1.9.2 Far-End Loopback
      10. 5.1.10 BIST
      11. 5.1.11 Cable Diagnostics
        1. 5.1.11.1 TDR
        2. 5.1.11.2 ALCD
    2. 5.2 Architecture
      1. 5.2.1 100Base-TX Transmit Path
        1. 5.2.1.1 MII Transmit Error Code Forwarding
        2. 5.2.1.2 4-Bit to 5-Bit Encoding
        3. 5.2.1.3 Scrambler
        4. 5.2.1.4 NRZI and MLT-3 Encoding
        5. 5.2.1.5 Digital to Analog Converter
      2. 5.2.2 100Base-TX Receive Path
        1. 5.2.2.1  Analog Front End
        2. 5.2.2.2  Adaptive Equalizer
        3. 5.2.2.3  Baseline Wander Correction
        4. 5.2.2.4  NRZI and MLT-3 Decoding
        5. 5.2.2.5  Descrambler
        6. 5.2.2.6  5B/4B Decoder and Nibble Alignment
        7. 5.2.2.7  Timing Loop and Clock Recovery
        8. 5.2.2.8  Phase-Locked Loops (PLL)
        9. 5.2.2.9  Link Monitor
        10. 5.2.2.10 Signal Detect
        11. 5.2.2.11 Bad SSD Detection
      3. 5.2.3 10Base-T Receive Path
        1. 5.2.3.1 10M Receive Input and Squelch
        2. 5.2.3.2 Collision Detection
        3. 5.2.3.3 Carrier Sense
        4. 5.2.3.4 Jabber Function
        5. 5.2.3.5 Automatic Link Polarity Detection and Correction
        6. 5.2.3.6 10Base-T Transmit and Receive Filtering
        7. 5.2.3.7 10Base-T Operational Modes
      4. 5.2.4 Auto Negotiation
        1. 5.2.4.1 Operation
        2. 5.2.4.2 Initialization and Restart
        3. 5.2.4.3 Next Page Support
      5. 5.2.5 Link Down Functionality
      6. 5.2.6 IEEE 1588 Precision Timing Protocol Support
    3. 5.3 Register Maps
      1. 5.3.1  Register Definition
        1. 5.3.1.1  Basic Mode Control Register (BMCR)
        2. 5.3.1.2  Basic Mode Status Register (BMSR)
        3. 5.3.1.3  PHY Identifier Register 1 (PHYIDR1)
        4. 5.3.1.4  PHY Identifier Register 2 (PHYIDR2)
        5. 5.3.1.5  Auto-Negotiation Advertisement Register (ANAR)
        6. 5.3.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
        7. 5.3.1.7  Auto-Negotiate Expansion Register (ANER)
        8. 5.3.1.8  Auto-Negotiate Next Page Transmit Register (ANNPTR)
        9. 5.3.1.9  Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
        10. 5.3.1.10 Control register 1 (CR1)
        11. 5.3.1.11 Control register 2 (CR2)
        12. 5.3.1.12 Control Register 3 (CR3)
        13. 5.3.1.13 Extended Register Addressing
          1. 5.3.1.13.1 Register Control Register (REGCR)
          2. 5.3.1.13.2 Address or Data Register (ADDAR)
        14. 5.3.1.14 Fast Link Down Status Register
        15. 5.3.1.15 PHY Status Register (PHYSTS)
        16. 5.3.1.16 PHY Specific Control Register (PHYSCR)
        17. 5.3.1.17 MII Interrupt Status Register 1 (MISR1)
        18. 5.3.1.18 MII Interrupt Status Register 2 (MISR2)
        19. 5.3.1.19 False Carrier Sense Counter Register (FCSCR)
        20. 5.3.1.20 Receiver Error Counter Register (RECR)
        21. 5.3.1.21 BIST Control Register (BISCR)
        22. 5.3.1.22 RMII Control and Status Register (RCSR)
        23. 5.3.1.23 LED Control Register (LEDCR)
        24. 5.3.1.24 PHY Control Register (PHYCR)
        25. 5.3.1.25 10Base-T Status/Control Register (10BTSCR)
        26. 5.3.1.26 BIST Control and Status Register 1 (BICSR1)
        27. 5.3.1.27 BIST Control and Status Register2 (BICSR2)
      2. 5.3.2  Cable Diagnostic Control Register (CDCR)
      3. 5.3.3  PHY Reset Control Register (PHYRCR)
      4. 5.3.4  Multi LED Control register (MLEDCR)
      5. 5.3.5  Compliance Test register (COMPTR)
      6. 5.3.6  IEEE1588 Precision Timing Pin Select (PTPPSEL)
      7. 5.3.7  IEEE1588 Precision Timing Configuration (PTPCFG)
      8. 5.3.8  TX_CLK Phase Shift Register (TXCPSR)
      9. 5.3.9  Power Back Off Control Register (PWRBOCR)
      10. 5.3.10 Voltage Regulator Control Register (VRCR)
      11. 5.3.11 Cable Diagnostic Configuration/Result Registers
        1. 5.3.11.1  ALCD Control and Results 1 (ALCDRR1)
        2. 5.3.11.2  Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
        3. 5.3.11.3  Cable Diagnostic Location Results Register 1 (CDLRR1)
        4. 5.3.11.4  Cable Diagnostic Location Results Register 2 (CDLRR2)
        5. 5.3.11.5  Cable Diagnostic Location Results Register 3 (DDLRR3)
        6. 5.3.11.6  Cable Diagnostic Location Results Register 4 (CDLRR4)
        7. 5.3.11.7  Cable Diagnostic Location Results Register 5 (CDLRR5)
        8. 5.3.11.8  Cable Diagnostic Amplitude Results Register 1 (CDARR1)
        9. 5.3.11.9  Cable Diagnostic Amplitude Results Register 2 (CDARR2)
        10. 5.3.11.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)
        11. 5.3.11.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)
        12. 5.3.11.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)
        13. 5.3.11.13 Cable Diagnostic General Results Register (CDGRR)
        14. 5.3.11.14 ALCD Control and Results 2 (ALCDRR2)
        15. 5.3.11.15 ALCD Control and Results 3 (ALCDRR3)
  6. 6Applications, Implementation, and Layout
    1. 6.1 Interfaces
      1. 6.1.1 Media Independent Interface (MII)
      2. 6.1.2 Reduced Media Independent Interface (RMII)
      3. 6.1.3 Serial Management Interface
        1. 6.1.3.1 Extended Address Space Access
          1. 6.1.3.1.1 Write Address Operation
          2. 6.1.3.1.2 Read Address Operation
          3. 6.1.3.1.3 Write (no post increment) Operation
          4. 6.1.3.1.4 Read (no post increment) Operation
          5. 6.1.3.1.5 Write (post increment) Operation
          6. 6.1.3.1.6 Read (post increment) Operation
    2. 6.2 Reset and Power-Down Operation
      1. 6.2.1 Hardware Reset
      2. 6.2.2 Software Reset
      3. 6.2.3 Power Down/Interrupt
        1. 6.2.3.1 Power Down Control Mode
        2. 6.2.3.2 Interrupt Mechanisms
      4. 6.2.4 Power Save Modes
    3. 6.3 Design Guidelines
      1. 6.3.1 TPI Network Circuit
      2. 6.3.2 Clock In (XI) Requirements
        1. 6.3.2.1 Oscillator
        2. 6.3.2.2 Crystal
      3. 6.3.3 Thermal Vias Recommendation
  7. 7Device and Documentation Support
    1. 7.1 Documentation Support
    2. 7.2 Related Links
    3. 7.3 Community Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

2 Revision History

Changes from C Revision (November 2014) to D Revision

  • Changed description of I/O Voltage Range and MAC interfaces to clarify voltages. Go
  • Changed QFN to VQFN Go
  • Added package informationGo
  • Added note for oscillator voltage levelsGo
  • Updated Handling Ratings to ESD Ratings and moved Storage temperature to Absolute Maximum RatingsGo
  • Added parameters for dual-supply operationGo
  • Changed Thermal Table format Go
  • Added timing parameter for XI clock stability after power up. Go
  • Deleted CLK25MHz_OUTGo
  • Added note on impact of enabling Enhanced LED link on link blinkingGo
  • Changed format of table header. Go
  • Added note that the default transmit link pulse polarity is reversedGo
  • Changed Register Block to Register Maps Go
  • Added Compliance Test register. Go
  • Changed format of Register Table header row. Go
  • Changed VRCR bits 3:0 to RESERVED. Go
  • Changed Speed Selection register bit to RWGo
  • Changed Auto-Negotiation Enable register bit to RWGo
  • Added Reserved bitsGo
  • Added note that enabling Enhanced LED Link overrides the LED blinking functionality of PHYCR register bit 5Go
  • Changed default to inverted polarity Go
  • Added text in MLEDCR clarifying polarity of LED. Go
  • Added Compliance Test register, address 0x0027 Go
  • Changed Power Back Off Levels Go
  • Changed VRCR bits 3:0 to RESERVED Go
  • Changed "the same levels as the MII interface" to "operates at 3.3V or 2.5V VDD_IO levels" Go
  • Deleted partial list of recommended transformers Go
  • Changed recommendation for common mode chokes to requirement. Go
  • Deleted the amplitude of the oscillator should be a nominal voltage of 3.3V. Go
  • Added notes on oscillator supply voltage.Go

Changes from B Revision (January 2014) to C Revision

  • Deleted "(TLK106)"Go
  • Deleted "IEEE 802.3u 100BASE-FX Fiber Interface"Go
  • Deleted "Additionally, the TLK10xL supports 100Base-FX signaling via an external optical transceiver."Go
  • Deleted "SD_IN"Go
  • Deleted Redundant row "Power dissipation 200 mW"Go
  • Deleted DC Characteristics, SD_INGo
  • VTH1 - max value deleted, 200-mV typ value addedGo
  • Deleted FX TimingGo
  • Deleted 25MHz_OUT Clock TimingGo
  • Deleted FIBCR RegisterGo
  • Deleted Fiber Mode Control 2 and Fiber Mode Control 3Go
  • Deleted Fiber Mode ControlGo
  • Deleted Fiber Mode Control Register, Fiber Mode Control 2 and Fiber Mode Control 3Go
  • Deleted Bit[14] Fiber Mode ControlGo
  • Changed "Active WOL" to "Active Energy Saving"Go
  • Changed "Passive WOL" to "Passive Energy Saving"Go
  • Changed "1" to "0"Go
  • Deleted Fiber Mode Control Register (FIBCR)Go
  • Deleted Fiber Mode Control Register 2 (FIBCR2)Go
  • Deleted Fiber Mode Control Register 3 (FIBCR3)Go
  • Changed "WOL (Wake-On LAN)" to "Energy Saving"Go
  • Changed "WOL (Wake-On LAN)" to "Energy Saving"Go

Changes from A Revision (November 2013) to B Revision

  • Changed "Low Power Consumption: <205mW PHY and 275mW with Center Tap (Typical)" to "Low Power Consumption: <126mW PHY and 200mW with Center Tap (Typical, dual supplies)"Go
  • Changed "MII and RMII Interfaces" to "MII and RMII Capabilities"Go
  • Changed "Error-Free Operation up to 150 Meters Under Typical Conditions" to "Error-Free 100Base-T Operation up to 150 Meters Under Typical Conditions Error-Free 10Base-T Operation up to 300 Meters Under Typical Conditions"Go
  • Added operating conditions for single and dual suppliesGo
  • Changed title from "Active Power" to "Active Power, Single Supply Operation"Go
  • Added Dual Supply Operation tableGo
  • Added bit 10, Fast Link Down Mode enable, Drop the link based on descrambler link loss, adusted description of bits 3:0 to reflect 5 options instead of 4Go
  • Deleted " Allow the system to reset the PHY using register access."Go
  • Changed recommended transformer from Pulse HX1188 to Pulse HX1198Go

Changes from * Revision (August 2013) to A Revision

  • Updated Pin Layout, changed "VDD33_IO" to "VDD_IO"Go
  • Added maximum storage temperatureGo
  • Changed "... stable for minimum of 1ms ..." to "... stable for minimum of 1µs ..." (typo correction)Go
  • Changed titles, "100Base-TX ... Timing" to "100Base-TX / FX ... Timing"Go
  • Added Power Back Off Control Register (0AEh)Go
  • Registers 0010h - 001Fh moved from extended-addressing space to direct-addressing spaceGo
  • Changed default value for MDL_REV from 0001 to 0010Go
  • Changed Default value of interrupt-polarity bit from 0 to 1 Go
  • Updated RMII Control and Status Register bit 4 descriptionGo