JAJSIE9E june   2021  – april 2023 TLV3601 , TLV3602 , TLV3603 , TLV3603E

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
      2. 7.4.2 Push-Pull (Single-Ended) Output
      3. 7.4.3 Known Startup Condition
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Hysteresis
      2. 8.1.2 Capacitive Loads
      3. 8.1.3 Latch Functionality
    2. 8.2 Typical Application
      1. 8.2.1 Implementing Hysteresis
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Optical Receiver
      3. 8.2.3 Over-Current Latch Condition
      4. 8.2.4 External Trigger Function for Oscilloscopes
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.3 Latch Functionality

The latch pin for the TLV3603(E) holds the output state of the device when the voltage at the LE/HYS pin is a logic low. This is particularly useful when the output state is intended to remain unchanged. An important consideration of the latch functionality is the latch hold and setup times. Latch hold time is the minimum time required (after the latch pin is asserted) for properly latching the comparator output. Likewise, latch setup time is defined as the time that the input must be stable before the latch pin is asserted low. The figure below illustrates when the input can transition for a valid latch. Note that the typical setup time in the EC table is negative; this is due to the internal trace delays of the LE/HYS pin relative to the input pin trace delays. A small delay (tPL) in the output response is shown below when the TLV3603(E) exits a latched output stage.

GUID-20210916-SS0I-VJ9V-M886-30ZVRNWVFZWL-low.svgFigure 8-3 Input Change Properly Latched
GUID-CF264D41-A3FE-48F0-BB40-62B7E61EBBC4-low.gifFigure 8-4 Latch Disable with Input Change