JAJSDS0 September   2017 TLV742P


  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Internal Current Limit
      2. 7.3.2 Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Input and Output Capacitor Requirements
        2. Dropout Voltage
        3. Transient Response
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 10.1.2 Package Mounting
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 評価モジュール
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報



Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The TLV742P is a LDO with low quiescent current that delivers excellent line and load transient performance. This LDO regulator offers current limit and thermal protection. The operating junction temperature of this device series is –40°C to +125°C.

Typical Application

TLV742P frontpg_app_SBVS323.gif Figure 44. Typical Application Circuit

Design Requirements

Provide an input supply with adequate headroom to meet minimum VIN requirements (as listed in Table 1), compensate for the GND pin current, and to power the load.

Table 1. Design Parameters

Input voltage 1.8 V to 3.6 V
Output voltage 1.2 V
Output current 100 mA

Detailed Design Procedure

Input and Output Capacitor Requirements

Generally, 1-µF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature.

However, the TLV742P is designed to be stable with an effective capacitance of 0.1 µF or larger at the output. As a result, the device is stable with capacitors of other dielectric types if the effective capacitance under operating bias voltage and temperature is greater than 0.1 µF. This effective capacitance refers to the capacitance that the LDO detects under operating bias voltage and temperature conditions; that is, the capacitance after taking bias voltage and temperature derating into consideration. In addition to using less expensive dielectrics, this stability with 0.1-µF effective capacitance enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications.

Using a 0.1-µF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions is less than 0.1 µF. Maximum ESR must be less than
200 mΩ.

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
1-µF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be required if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2-Ω, a 0.1-µF input capacitor may be required to ensure stability.

Dropout Voltage

The TLV742P series of LDOs use a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device functions similar to a resistor in dropout.

PSRR and transient response degrade when (VIN – VOUT) approaches dropout.

Transient Response

Increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases the duration of the transient response.

Application Curves

TLV742P tc_psrr-frq_12v_bvs153.gif
VOUT = 1.2 V
Figure 45. Power-Supply Ripple Rejection vs Frequency
TLV742P tc_load_12v_1-150_bvs153.gif
VOUT = 1.2 V
Figure 47. Load Transient Response
TLV742P tc_line_12v_200ma_A_bvs153.gif
VOUT = 1.2 V, IOUT = 200 mA
Figure 49. Line Transient Response
TLV742P tc_line_12v_200ma_B_bvs153.gif
VOUT = 1.2 V, IOUT = 200 mA
Figure 51. Line Transient Response
TLV742P tc_noise-frq_bvs244.gif
Figure 46. Output Spectral Noise Density vs Frequency
TLV742P tc_line_12v_150ma_A_bvs153.gif
VOUT = 1.2 V, IOUT = 150 mA
Figure 48. Line Transient Response
TLV742P tc_line_12v_150ma_B_bvs153.gif
VOUT = 1.2 V, IOUT = 150 mA
Figure 50. Line Transient Response
TLV742P tc_ramp_up_down_bvs153.gif
VOUT = 1.2 V, IOUT = 30 mA
Figure 52. VIN Ramp Up, Ramp Down Response

Do's and Don'ts

Place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator.

Do not place the output capacitor more than 10 mm away from the regulator.

Connect a 1-µF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator for improved transient performance.

Do not exceed the absolute maximum ratings.