JAJSE80R October   2017  – November 2021 TLV9001 , TLV9002 , TLV9004

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 説明
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TLV9001
    5. 7.5  Thermal Information: TLV9001S
    6. 7.6  Thermal Information: TLV9002
    7. 7.7  Thermal Information: TLV9002S
    8. 7.8  Thermal Information: TLV9004
    9. 7.9  Thermal Information: TLV9004S
    10. 7.10 Electrical Characteristics
    11. 7.11 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Input
      3. 8.3.3 Rail-to-Rail Output
      4. 8.3.4 EMI Rejection
    4. 8.4 Overload Recovery
    5. 8.5 Shutdown
    6. 8.6 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV900x Low-Side, Current Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Single-Supply Photodiode Amplifier
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Input and ESD Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RUC|14
  • D|14
  • DYY|14
  • PW|14
  • RTE|16
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

For VS = (V+) – (V–) = 1.8 V to 5.5 V (±0.9 V to ±2.75 V), TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT =
VS / 2 (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
OFFSET VOLTAGE
VOSInput offset voltageVS = 5 V±0.4±1.6mV
VS = 5 V, TA = –40°C to 125°C±2
dVOS/dTVOS vs temperatureTA = –40°C to 125°C±0.6µV/°C
PSRRPower-supply rejection ratioVS = 1.8 to 5.5 V, VCM = (V–)80105dB
INPUT VOLTAGE RANGE
VCMCommon-mode voltage rangeNo phase reversal, rail-to-rail input(V–) – 0.1(V+) + 0.1V
CMRRCommon-mode rejection ratioVS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
86dB
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to 125°C
95
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to 125°C
6377
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to 125°C
68
INPUT BIAS CURRENT
IBInput bias currentVS = 5 V±5pA
IOSInput offset current±2pA
NOISE
EnInput voltage noise (peak-to-peak)ƒ = 0.1 Hz to 10 Hz, VS = 5 V4.7µVPP
enInput voltage noise densityƒ = 1 kHz, VS = 5 V30nV/√ Hz
ƒ = 10 kHz, VS = 5 V27
inInput current noise densityƒ = 1 kHz, VS = 5 V23fA/√ Hz
INPUT CAPACITANCE
CIDDifferential1.5pF
CICCommon-mode5pF
OPEN-LOOP GAIN
AOLOpen-loop voltage gainVS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ
104117dB
VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ
100
VS = 1.8 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 2 kΩ
115
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ
130
FREQUENCY RESPONSE
GBWGain-bandwidth productVS = 5 V1MHz
φmPhase marginVS = 5.5 V, G = 178°
SRSlew rateVS = 5 V2V/µs
tSSettling timeTo 0.1%, VS = 5 V, 2-V step, G = +1, CL = 100 pF2.5µs
To 0.01%, VS = 5 V, 2-V step, G = +1, CL = 100 pF3
tOROverload recovery timeVS = 5 V, VIN × gain > VS0.85µs
THD+NTotal harmonic distortion + noiseVS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1,
ƒ = 1 kHz, 80-kHz measurement BW
0.004%
OUTPUT
VOVoltage output swing from supply railsVS = 5.5 V, RL = 10 kΩ1020mV
VS = 5.5 V, RL = 2 kΩ3555
ISCShort-circuit currentVS = 5.5 V±40mA
ZOOpen-loop output impedanceVS = 5 V, ƒ = 1 MHz1200Ω
POWER SUPPLY
VSSpecified voltage range1.8 (±0.9)5.5 (±2.75)V
IQQuiescent current per amplifierTLV9002, TLV9002S TLV9004, TLV9004SIO = 0 mA, VS = 5.5 V6075µA
TLV9001, TLV9001SIO = 0 mA, VS = 5.5 V6077
IO = 0 mA, VS = 5.5 V, TA = –40°C to 125°C85
SHUTDOWN(1)
IQSDQuiescent current per amplifierVS = 1.8 V to 5.5 V, all amplifiers disabled, SHDN = VS0.51.5µA
ZSHDNOutput impedance during shutdownVS = 1.8 V to 5.5 V, amplifier disabled10 || 2GΩ || pF
High level voltage shutdown threshold (amplifier enabled)VS = 1.8 V to 5.5 V(V–) + 0.9(V–) + 1.1V
Low level voltage shutdown threshold (amplifier disabled)VS = 1.8 V to 5.5 V(V–) + 0.2 V(V–) + 0.7 VV
tONAmplifier enable time (full shutdown)VS = 1.8 V to 5.5 V, full shutdown; G = 1,
VOUT = 0.9 × VS / 2, RL connected to V–
70µs
Amplifier enable time (partial shutdown)VS = 1.8 V to 5.5 V, partial shutdown; G = 1,
VOUT = 0.9 × VS / 2, RL connected to V–
50
tOFFAmplifier disable timeVS = 1.8 V to 5.5 V, G = 1, VOUT = 0.1 × VS / 2,
RL connected to V–
4µs
SHDN pin input bias current (per pin)VS = 1.8 V to 5.5 V, V+ ≥ SHDN ≥ (V+) – 0.8 V40nA
VS = 1.8 V to 5.5 V, V– ≤ SHDN ≤ V– + 0.8 V150
Specified by design and characterization; not production tested.