JAJSGR1E October 2014 – September 2021 TMP102-Q1
The TMP102-Q1 device supports the SMBus alert function. When the TMP102-Q1 device operates in Interrupt Mode (TM = 1), the ALERT pin can be connected as an SMBus alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus alert command (0001 1001) to the bus. If the ALERT pin is active, the device acknowledges the SMBus alert command and responds by returning the slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the ALERT condition was caused by the temperature exceeding THIGH or falling below TLOW. For POL = 0, the LSB is low if the temperature is greater than or equal to THIGH; this bit is high if the temperature is less than TLOW. The polarity of this bit is inverted if POL = 1. See Figure 7-5 for details of this sequence.
If multiple devices on the bus respond to the SMBus alert command, arbitration during the slave address portion of the SMBus alert command determines which device clears the ALERT status. The device with the lowest two-wire address wins the arbitration. If the TMP102-Q1 device wins the arbitration, its ALERT pin inactivates at the completion of the SMBus alert command. If the TMP102-Q1 device loses the arbitration, its ALERT pin remains active.