JAJSIR1B March   2020  – December 2020 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1. 3.1 機能ブロック図
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pin Multiplexing
      1. 6.4.1 GPIO Muxed Pins
        1. 6.4.1.1 GPIO Muxed Pins Table
      2. 6.4.2 Digital Inputs on ADC Pins (AIOs)
      3. 6.4.3 GPIO Input X-BAR
      4. 6.4.4 GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
    5. 6.5 Pins With Internal Pullup and Pulldown
    6. 6.6 Connections for Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5.     Supply Voltages
    6. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
        1. 7.5.4.1 Typical Current Reduction per Disabled Peripheral
    7. 7.6  Electrical Characteristics
    8. 7.7  Thermal Resistance Characteristics for PN Package
    9. 7.8  Thermal Resistance Characteristics for PM Package
    10. 7.9  Thermal Resistance Characteristics for PT Package
    11. 7.10 Thermal Design Considerations
    12. 7.11 System
      1. 7.11.1 Power Management
        1. 7.11.1.1 Internal 1.2-V LDO Voltage Regulator (VREG)
        2. 7.11.1.2 Power Sequencing
        3. 7.11.1.3 Power-On Reset (POR)
        4. 7.11.1.4 Brownout Reset (BOR)
      2. 7.11.2 Reset Timing
        1. 7.11.2.1 Reset Sources
        2. 7.11.2.2 Reset Electrical Data and Timing
          1. 7.11.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.11.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.11.2.2.3 Reset Timing Diagrams
      3. 7.11.3 Clock Specifications
        1. 7.11.3.1 Clock Sources
        2. 7.11.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.11.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.11.3.2.1.1 Input Clock Frequency
            2. 7.11.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.11.3.2.1.3 X1 Timing Requirements
            4. 7.11.3.2.1.4 APLL Characteristics
            5. 7.11.3.2.1.5 XCLKOUT Switching Characteristics
            6. 7.11.3.2.1.6 Internal Clock Frequencies
        3. 7.11.3.3 Input Clocks and PLLs
        4. 7.11.3.4 Crystal Oscillator
          1. 7.11.3.4.1 Crystal Oscillator Parameters
          2. 7.11.3.4.2 Crystal Oscillator Electrical Characteristics
        5. 7.11.3.5 Internal Oscillators
          1. 7.11.3.5.1 INTOSC Characteristics
      4. 7.11.4 Flash Parameters
      5. 7.11.5 Emulation/JTAG
        1. 7.11.5.1 JTAG Electrical Data and Timing
          1. 7.11.5.1.1 JTAG Timing Requirements
          2. 7.11.5.1.2 JTAG Switching Characteristics
          3. 7.11.5.1.3 JTAG Timing Diagram
        2. 7.11.5.2 cJTAG Electrical Data and Timing
          1. 7.11.5.2.1 cJTAG Timing Requirements
          2. 7.11.5.2.2 cJTAG Switching Characteristics
          3. 7.11.5.2.3 cJTAG Timing Diagram
      6. 7.11.6 GPIO Electrical Data and Timing
        1. 7.11.6.1 GPIO – Output Timing
          1. 7.11.6.1.1 General-Purpose Output Switching Characteristics
        2. 7.11.6.2 GPIO – Input Timing
          1. 7.11.6.2.1 General-Purpose Input Timing Requirements
          2. 7.11.6.2.2 Sampling Mode
        3. 7.11.6.3 Sampling Window Width for Input Signals
      7. 7.11.7 Interrupts
        1. 7.11.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.11.7.1.1 External Interrupt Timing Requirements
          2. 7.11.7.1.2 External Interrupt Switching Characteristics
          3. 7.11.7.1.3 External Interrupt Timing
      8. 7.11.8 Low-Power Modes
        1. 7.11.8.1 Clock-Gating Low-Power Modes
        2. 7.11.8.2 Low-Power Mode Wake-up Timing
          1. 7.11.8.2.1 IDLE Mode Timing Requirements
          2. 7.11.8.2.2 IDLE Mode Switching Characteristics
          3. 7.11.8.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.11.8.2.4 STANDBY Mode Timing Requirements
          5. 7.11.8.2.5 STANDBY Mode Switching Characteristics
          6. 7.11.8.2.6 STANDBY Entry and Exit Timing Diagram
          7. 7.11.8.2.7 HALT Mode Timing Requirements
          8. 7.11.8.2.8 HALT Mode Switching Characteristics
          9. 7.11.8.2.9 HALT Entry and Exit Timing Diagram
    13. 7.12 Analog Peripherals
      1.      Analog Pins and Internal Connections
      2.      Analog Signal Descriptions
      3. 7.12.1 Analog-to-Digital Converter (ADC)
        1. 7.12.1.1 ADC Configurability
          1. 7.12.1.1.1 Signal Mode
        2. 7.12.1.2 ADC Electrical Data and Timing
          1. 7.12.1.2.1 ADC Operating Conditions
          2. 7.12.1.2.2 ADC Characteristics
          3. 7.12.1.2.3 ADC Input Model
          4. 7.12.1.2.4 ADC Timing Diagrams
      4. 7.12.2 Temperature Sensor
        1. 7.12.2.1 Temperature Sensor Electrical Data and Timing
          1. 7.12.2.1.1 Temperature Sensor Characteristics
      5. 7.12.3 Comparator Subsystem (CMPSS)
        1. 7.12.3.1 CMPSS Electrical Data and Timing
          1. 7.12.3.1.1 Comparator Electrical Characteristics
          2.        CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.12.3.1.2 CMPSS DAC Static Electrical Characteristics
          4. 7.12.3.1.3 CMPSS Illustrative Graphs
    14. 7.13 Control Peripherals
      1. 7.13.1 Enhanced Pulse Width Modulator (ePWM)
        1. 7.13.1.1 Control Peripherals Synchronization
        2. 7.13.1.2 ePWM Electrical Data and Timing
          1. 7.13.1.2.1 ePWM Timing Requirements
          2. 7.13.1.2.2 ePWM Switching Characteristics
          3. 7.13.1.2.3 Trip-Zone Input Timing
            1. 7.13.1.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.13.1.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.13.1.3.1 External ADC Start-of-Conversion Switching Characteristics
      2. 7.13.2 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.13.2.1 HRPWM Electrical Data and Timing
          1. 7.13.2.1.1 High-Resolution PWM Characteristics
      3. 7.13.3 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.13.3.1 High-Resolution Capture (HRCAP)
        2.       eCAP and HRCAP Block Diagram
        3. 7.13.3.2 eCAP/HRCAP Synchronization
        4. 7.13.3.3 eCAP Electrical Data and Timing
          1. 7.13.3.3.1 eCAP Timing Requirements
          2. 7.13.3.3.2 eCAP Switching Characteristics
        5. 7.13.3.4 HRCAP Electrical Data and Timing
          1. 7.13.3.4.1 HRCAP Switching Characteristics
          2.        HRCAP Figure and Graph
      4. 7.13.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.13.4.1 eQEP Electrical Data and Timing
          1. 7.13.4.1.1 eQEP Timing Requirements
          2. 7.13.4.1.2 eQEP Switching Characteristics
    15. 7.14 Communications Peripherals
      1. 7.14.1 Controller Area Network (CAN)
      2. 7.14.2 Inter-Integrated Circuit (I2C)
        1. 7.14.2.1 I2C Electrical Data and Timing
          1. 7.14.2.1.1 I2C Timing Requirements
          2. 7.14.2.1.2 I2C Switching Characteristics
          3. 7.14.2.1.3 I2C Timing Diagram
      3. 7.14.3 Power Management Bus (PMBus) Interface
        1. 7.14.3.1 PMBus Electrical Data and Timing
          1. 7.14.3.1.1 PMBus Electrical Characteristics
          2. 7.14.3.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.14.3.1.3 PMBus Standard Mode Switching Characteristics
      4. 7.14.4 Serial Communications Interface (SCI)
      5. 7.14.5 Serial Peripheral Interface (SPI)
        1. 7.14.5.1 SPI Master Mode Timings
          1. 7.14.5.1.1 SPI Master Mode Timing Requirements
          2. 7.14.5.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
          3. 7.14.5.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
          4. 7.14.5.1.4 SPI Master Mode Timing Diagrams
        2. 7.14.5.2 SPI Slave Mode Timings
          1. 7.14.5.2.1 SPI Slave Mode Timing Requirements
          2. 7.14.5.2.2 SPI Slave Mode Switching Characteristics
          3. 7.14.5.2.3 SPI Slave Mode Timing Diagrams
      6. 7.14.6 Local Interconnect Network (LIN)
      7. 7.14.7 Fast Serial Interface (FSI)
        1. 7.14.7.1 FSI Transmitter
          1. 7.14.7.1.1 FSITX Electrical Data and Timing
            1. 7.14.7.1.1.1 FSITX Switching Characteristics
            2. 7.14.7.1.1.2 FSITX Timings
        2. 7.14.7.2 FSI Receiver
          1. 7.14.7.2.1 FSIRX Electrical Data and Timing
            1. 7.14.7.2.1.1 FSIRX Timing Requirements
            2. 7.14.7.2.1.2 FSIRX Switching Characteristics
            3. 7.14.7.2.1.3 FSIRX Timings
        3. 7.14.7.3 FSI SPI Compatibility Mode
          1. 7.14.7.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.14.7.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.14.7.3.1.2 FSITX SPI Signaling Mode Timings
      8. 7.14.8 Host Interface Controller (HIC)
        1. 7.14.8.1 HIC Electrical Data and Timing
          1. 7.14.8.1.1 HIC Timing Requirements
          2. 7.14.8.1.2 HIC Switching Characteristics
          3. 7.14.8.1.3 HIC Timing Diagrams
  8. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  Functional Block Diagram
    3. 8.3  Memory
      1. 8.3.1 Memory Map
        1. 8.3.1.1 Dedicated RAM (Mx RAM)
        2. 8.3.1.2 Local Shared RAM (LSx RAM)
        3. 8.3.1.3 Global Shared RAM (GSx RAM)
      2. 8.3.2 Flash Memory Map
        1. 8.3.2.1 Addresses of Flash Sectors
      3. 8.3.3 Peripheral Registers Memory Map
    4. 8.4  Identification
    5. 8.5  Bus Architecture – Peripheral Connectivity
    6. 8.6  C28x Processor
      1. 8.6.1 Floating-Point Unit (FPU)
      2. 8.6.2 Fast Integer Division Unit
      3. 8.6.3 Trigonometric Math Unit (TMU)
      4. 8.6.4 VCRC Unit
    7. 8.7  Embedded Real-Time Analysis and Diagnostic (ERAD)
    8. 8.8  Background CRC-32 (BGCRC)
    9. 8.9  Direct Memory Access (DMA)
    10. 8.10 Device Boot Modes
      1. 8.10.1 Device Boot Configurations
        1. 8.10.1.1 Configuring Boot Mode Pins
        2. 8.10.1.2 Configuring Boot Mode Table Options
      2. 8.10.2 GPIO Assignments
    11. 8.11 Dual Code Security Module
    12. 8.12 Watchdog
    13. 8.13 C28x Timers
    14. 8.14 Dual-Clock Comparator (DCC)
      1. 8.14.1 特長
      2. 8.14.2 Mapping of DCCx (DCC0 and DCC1) Clock Source Inputs
    15. 8.15 Configurable Logic Block (CLB)
  9. 9 Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device and Development Support Tool Nomenclature
    3. 10.3 Markings
    4. 10.4 Tools and Software
    5. 10.5 Documentation Support
    6. 10.6 サポート・リソース
    7. 10.7 Trademarks
    8. 10.8 静電気放電に関する注意事項
    9. 10.9 用語集
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Revision History

Changes from October 4, 2020 to December 31, 2020 (from Revision A (October 2020) to Revision B (December 2020))

  • グローバル：TMS320F280025-Q1、TMS320F280025C-Q1、TMS320F280023-Q1、TMS320F280021-Q1 を追加。Go
  • 表 5-1 (デバイスの比較)：TMS320F280025-Q1、TMS320F280025C-Q1、TMS320F280023-Q1、TMS320F280021-Q1 を追加。表を更新。Go
  • Table 6-1 (Pin Attributes): Updated muxed signal names of A7. Updated DESCRIPTION of VDD: Changed recommended total capacitance from 22 µF to 10 µF.Go
  • Removed Digital Signals by GPIO section (Section 6.3.2 in SPRSP45A).Go
  • Section 6.3.2 (Digital Signals): Added section.Go
  • Table 6-4 (Power and Ground): Updated DESCRIPTION of VDD: Changed recommended total capacitance from 22 µF to 10 µF.Go
  • Section 7.2 (ESD Ratings – Commercial): Updated device numbers.Go
  • Section 7.3 (ESD Ratings – Automotive): Updated device numbers. Added data for 64-pin PM package.Go
  • Section 7.5.1 (System Current Consumption): Updated table.Go
  • Section 7.11.1.1 (Internal 1.2-V LDO Voltage Regulator (VREG)): Updated Configuration 1.Go
  • Section 7.11.3.5.1 (INTOSC Characteristics): Updated table.Go
  • Table 7-5 (Flash Parameters): Changed "Nwec Write/Erase Cycles" to "Nwec Write/Erase Cycles per sector". Added "Nwec Write/Erase Cycles for entire Flash (combined all sectors)".Go
  • Section 7.14.8 (Host Interface Controller (HIC)): Updated "The HIC module allows ..." paragraph.Go
  • Figure 7-70 (HIC Block Diagram): Removed "Bus Master Interface" label.Go
  • Figure 10-1 (Device Nomenclature): Updated figure.Go
  • Section 10.4 (Tools and Software): Added LAUNCHXL-F280025C to Development Tools section.Go

Changes from March 17, 2020 to October 3, 2020 (from Revision * (March 2020) to Revision A (October 2020))

  • グローバル：文書全体にわたって表、図、相互参照の採番方法を更新Go
  • グローバル：このドキュメントは現在「量産データ」です。Go
  • グローバル：TMS320F280024、TMS320F280024C、TMS320F280022 を削除。Go
  • グローバル：64 QFP-Q のデータを削除。Go
  • Section 1 (特長)：SCI (Serial Communication Interface) の特長を更新。LIN (Local Interconnect Network) の特長を更新。Go
  • 表 5-1 (デバイスの比較)：表を更新。Go
  • Section 2 (アプリケーション)：セクションを更新。Go
  • Section 3 (概要)：セクションを更新。Go
  • 製品情報：表を更新。Go
  • 図 3-1 (機能ブロック図)：図を更新。Go
  • Table 6-1 (Pin Attributes): Updated table.Go
  • Figure 6-2 (64-Pin PM Low-Profile Quad Flatpack (Top View)): Updated figure.Go
  • Removed "64-Pin PM Low-Profile Quad Flatpack – Q-Temperature (Top View)" figure.Go
  • Removed Digital Signals section (Section 4.3.2 in SPRSP45).Go
  • Digital Signals by GPIO: Added section.Go
  • Table 6-4 (Power and Ground): Updated DESCRIPTION of VDD and VDDIO.Go
  • Section 6.4.1.1 (GPIO Muxed Pins Table): Added Note about AIO pins.Go
  • Table 6-6 (GPIO Muxed Pins): Updated table.Go
  • Section 6.4.4 (GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR): Changed section title from "GPIO Output X-BAR and ePWM X-BAR" to "GPIO Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR". Updated section.Go
  • Figure 6-5 (Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources): Replaced "Output X-BAR and ePWM X-BAR Sources" figure with "Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR Sources" figure.Go
  • Table 6-9 (Connections for Unused Pins): Added "Analog input pins" in ANALOG section.Go
  • Section 7 (Specifications): Updated section and tables.Go
  • Section 7.1 (Absolute Maximum Ratings): Updated table.Go
  • Section 7.4 (Recommended Operating Conditions): Updated SRSUPPLY values and unit.Go
  • Section 7.6 (Electrical Characteristics): Updated ROH and ROL values.Go
  • Section 7.3 (ESD Ratings – Automotive): Removed F280024, F280024C, and F280022 data.Go
  • Section 7.5.3 (Current Consumption Graphs): Added section.Go
  • Section 7.5.4 (Reducing Current Consumption): Updated section.Go
  • Section 7.5.4.1 (Typical Current Reduction per Disabled Peripheral): Updated table.Go
  • Section 7.7 (Thermal Resistance Characteristics for PN Package): Added section.Go
  • Section 7.8 (Thermal Resistance Characteristics for PM Package): Added section.Go
  • Section 7.9 (Thermal Resistance Characteristics for PT Package): Added section.Go
  • Section 7.11.2.2.1 (Reset (XRSn) Timing Requirements): Updated tw(RSL2).Go
  • Section 7.11.2.2.2 (Reset (XRSn) Switching Characteristics): Added tboot-flash.Go
  • Figure 7-8 (Power-on Reset): Updated figure.Go
  • Section 7.11.3.2.1.6 (Internal Clock Frequencies): Updated MAX f(VCOCLK).Go
  • Section 7.11.3.5 (Internal Oscillators): Updated section.Go
  • Section 7.11.3.5.1 (INTOSC Characteristics): Updated fINTOSC MIN values and MAX values.Go
  • Section 7.11.4 (Flash Parameters): Updated section.Go
  • Table 7-4 (Minimum Required Flash Wait States with Different Clock Sources and Frequencies): Updated table and footnotes.Go
  • Table 7-5 (Flash Parameters): Added "The on-chip flash memory is in an erased state ..." footnote.Go
  • Section 7.11.5 (Emulation/JTAG): Updated link of Hardware Breakpoints and Watchpoints for C28x in CCS.Go
  • Figure 7-31 (Analog Group Connections): Added figure.Go
  • Figure 7-35 (ADC Timings): Updated tINT.Go
  • Section 7.14.2.1.1 (I2C Timing Requirements): Updated table.Go
  • Section 7.14.2.1.2 (I2C Switching Characteristics): Updated table.Go
  • Figure 7-54 (I2C Timing Diagram): Added figure.Go
  • Figure 7-56 (SCI Block Diagram): Updated figure.Go
  • Figure 7-59 (SPI Master Mode External Timing (Clock Phase = 1)): Updated parameter 24.Go
  • Section 7.14.5.2.1 (SPI Slave Mode Timing Requirements): Updated MIN value of tsu(STE)S.Go
  • Section 7.14.8 (Host Interface Controller (HIC)): Updated list of features.Go
  • Figure 7-70 (HIC Block Diagram): Updated figure.Go
  • Section 7.14.8.1.1 (HIC Timing Requirements): Updated table.Go
  • Section 7.14.8.1.2 (HIC Switching Characteristics): Updated table.Go
  • Figure 7-71 (Read/Write Operation With nOE and nWE Pins): Added figure.Go
  • Figure 7-72 (Read/Write Operation With RnW Pin): Added figure.Go
  • Figure 8-1 (Functional Block Diagram): Added "Secure Memories shown in Red" legend box.Go
  • Table 8-2 (Addresses of Flash Sectors): Updated table.Go
  • Table 8-4 (Device Identification Registers): Removed PARTIDH for TMS320F280024, TMS320F280024C, and TMS320F280022.Go
  • Table 8-4: Added REVID for Revision A silicon.Go
  • Table 8-4: Updated ADDRESS of UID_UNIQUE.Go
  • Section 8.10 (Device Boot Modes): Updated section.Go
  • Section 8.10.1 (Device Boot Configurations): Added Note about CAN boot mode turning on the XTAL.Go
  • Figure 8-3 (Windowed Watchdog): Removed SCSR.WDOVERRIDE.Go
  • Section 9.1 (TI Reference Design): Updated section.Go
  • Removed Related Links section (Section 10.5 in SPRSP45).Go
  • Section 10.1 (Getting Started and Next Steps): Added section.Go
  • Section 10.2 (Device and Development Support Tool Nomenclature): Updated section.Go
  • Figure 10-1 (Device Nomenclature): Removed 280024, 280024C, and 280022 from DEVICE.Go
  • Figure 10-2 (Package Symbolization for PM and PN Packages): Updated figure.Go
  • Figure 10-3 (Package Symbolization for PT Package): Updated figure.Go
  • Table 10-1 (Revision Identification): Added data for Revision A silicon.Go
  • Section 10.4 (Tools and Software): Updated section.Go
  • Section 10.5 (Documentation Support): Updated section.Go