SLASEW5 December   2020 TMUXHS4412

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
      2. 7.3.2 Data Line Biasing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Lane Muxing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
    3. 8.3 Systems Examples
      1. 8.3.1 PCIe Muxing for Hybrid SSD
      2. 8.3.2 DisplayPort Main Link
      3. 8.3.3 USB 4.0 / TBT 3.0 Demuxing
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

PCIe Lane Muxing

The TMUXHS4412 can be used to switch PCIe lanes between two slots. In many PC and server motherboards, the CPU does not have enough PCIe lanes to provide desired system flexibility for end customers. In such applications, the TMUXHS4412 can be used to switch PCIe TX and RX lanes between two slots. Figure 8-2 provides a schematic where four TMUXHS4412 are used to switch eight PCIe lanes (8-TX and 8-RX channels). Note the common mode voltage (CMV) bias for the TMUXHS4412 must be within the valid range. In implementations where receiver CMV bias of a PCIe root complex or an end point can not be ensured within the CMV range, additional DC blocking capacitors and appropriate CMV biasing must be implemented. One side of the device has AC coupling capacitors. Additionally the PD pin must be low for device to work. This pin can be driven by a processor.

GUID-20201120-CA0I-HP2X-QFQV-X7MJTF19Q7TP-low.gif Figure 8-2 PCIe Lane Muxing