JAJSKW6 december   2020 TMUXHS4412

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
      2. 7.3.2 Data Line Biasing
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Lane Muxing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
    3. 8.3 Systems Examples
      1. 8.3.1 PCIe Muxing for Hybrid SSD
      2. 8.3.2 DisplayPort Main Link
      3. 8.3.3 USB 4.0 / TBT 3.0 Demuxing
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.8 Typical Characteristics

Figure 6-1 shows differential insertion loss on the top plot and return loss on the bottom plot of a typical TMUXHS4412 channel. Note measurements are performed in TI evaluation board with board and equipment parasitics calibrated out.
GUID-20201210-CA0I-VHBB-8WGT-VN65HNP3BBQG-low.gif Figure 6-1 S-parameter plots for a TMUXHS4412 channel - top: differential insertion loss, and bottom: return loss vs frequency
Figure 6-2 shows side by side comparison of 10 Gbps signals through calibration traces and a typical TMUXHS4412 channels.
GUID-20201203-CA0I-WCWD-DGTJ-5M4B7P4CLB5J-low.jpg GUID-20201203-CA0I-RG3X-LFRG-XBBCMNNKM3C8-low.jpg Figure 6-2 Jitter decomposition of 10 Gbps PRBS-7 signals in TI evaluation board - Top: through calibration traces, Bottom: through a typical TMUXHS4412 channels
Figure 6-3 shows side by side comparison of 20 Gbps signals through calibration traces and a typical TMUXHS4412 channels.
GUID-20201203-CA0I-JFCL-MGBC-1WRS1GWMJRWZ-low.jpg GUID-20201203-CA0I-N8NF-VQW9-CVCCCWMTNSWH-low.jpg Figure 6-3 Jitter decomposition of 20 Gbps PRBS-7 signals in TI evaluation board - Top: through calibration traces, Bottom: through a typical TMUXHS4412 channels