SLASEW5 December   2020 TMUXHS4412

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable and Power Savings
      2. 7.3.2 Data Line Biasing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 PCIe Lane Muxing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Pin-to-pin Passive versus Redriver Option
        4. 8.2.1.4 Application Curves
    3. 8.3 Systems Examples
      1. 8.3.1 PCIe Muxing for Hybrid SSD
      2. 8.3.2 DisplayPort Main Link
      3. 8.3.3 USB 4.0 / TBT 3.0 Demuxing
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Electrical Characteristics

over operating free-air temperature and supply voltage range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Device active current PD = 0; 0 V ≤ VCM ≤ 1.8; SEL = 0 or VCC 320 480 µA
ISTDN Device shutdown current PD = VCC 0.1 2 µA
CON Output ON capacitance to GND PD = 0; f =  8 Ghz 0.45 pF
RON Output ON resistance 0 V ≤ VCM ≤ 1.8 V; IO = –8 mA 5 8 Ω
IIH,CTRL Input high current, control pins (SEL, PD) VIN = 3.6 V 2 µA
IIL,CTRL Input low current, control pins (SEL, PD) VIN = 0 V 1 µA
RCM,HS Common mode resistance to ground on D pins (Dx[P/N]) Each pin to GND 1.0 1.4
IIH,HS,SEL Input high current, high-speed pins [Dx/DAx/DBx][P/N] VIN = 1.8 V for selected port, D and DA pins with SEL = 0, and D and DB pins with SEL = VCC 5 µA
IIH,HS,NSEL Input high current, high-speed pins [Dx/DAx/DBx][P/N] VIN = 1.8 V for non-selected port, DB with SEL = 0, and DA with SEL = VCC (1) 150 µA
IHIZ,HS Leakage current through turned off switch between Dx[P/N] and [DA/DB]x[P/N] PD = VCC; Dx[P/N] = 1.8 V, [DA/DB]x[P/N] = 0 V and Dx[P/N] = 0 V, [DA/DB]x[P/N] = 1.8 V 4 µA
RA,p2n DC Impedance between Dx[P] and Dx[N] pins PD = 0 and VCC 20
There is a 20-kΩ pull-down in non-selected port.