JAJSHS8E June   2011  – August 2019 TPA6211A1-Q1

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      アプリケーション回路
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Operating Characteristics
    7. 6.7 Dissipation Ratings
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Advantages of Fully Differential Amplifiers
      2. 7.3.2 Fully Differential Amplifier Efficiency and Thermal Information
      3. 7.3.3 Differential Output Versus Single-Ended Output
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Differential Input Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Resistors (RI)
          2. 8.2.1.2.2 Bypass Capacitor (CBYPASS) and Start-Up Time
          3. 8.2.1.2.3 Input Capacitor (CI)
          4. 8.2.1.2.4 Band-Pass Filter (RI, CI, and CF)
            1. 8.2.1.2.4.1 Step 1: Low-Pass Filter
            2. 8.2.1.2.4.2 Step 2: High-Pass Filter
            3. 8.2.1.2.4.3 Step 3: Additional Low-Pass Filter
          5. 8.2.1.2.5 Decoupling Capacitor (CS)
          6. 8.2.1.2.6 Using Low-ESR Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Other Application Circuits
  9. Power Supply Recommendations
    1. 9.1 Power Supply Decoupling Capacitor
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Bypass Capacitor (CBYPASS) and Start-Up Time

The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to VDD / 2. Adding a capacitor filters any noise into this pin, increasing kSVR. CBYPASS also determines the rise time of VO+ and VO– when the device exits shutdown. The larger the capacitor, the slower the rise time.