SLVSC54B July   2013  – April 2014 TPD4E110

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Terminal Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Signal range on Terminal 1, 2, 3, or 4
        2. 9.2.2.2 Operating Frequency
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Single Layer Routing
      2. 10.2.2 Double Layer Routing
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Operating temperature range -40 125 °C
IPP Peak pulse current (tp = 8/20μs) 2.5 A
PPP(forward) Peak pulse power (tp = 8/20μs) 35 W
PPP(reverse) Peak pulse power (tp = 8/20μs) 18 W
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature –65 155 °C
ESD(1) IEC 61000-4-2 contact ESD ±12 kV
IEC 61000-4-2 air-gap ESD ±15 kV
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in to the device.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIO 0.0 5.5 V
TA Operating free-air temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPD4E110 UNIT
DPW
(4 TERMINALS)
RθJA Junction-to-ambient thermal resistance 291.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 224.2
RθJB Junction-to-board thermal resistance 245.8
ψJT Junction-to-top characterization parameter 31.4
ψJB Junction-to-board characterization parameter 245.6
RθJC(bot) Junction-to-case (bottom) thermal resistance 195.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VRWM Reverse stand-off voltage IIO = 10 μA 5.5 V
VCLAMP Clamp voltage with ESD strike I = 1A, TLP, I/O to GND 10 V
I = 5A, TLP, I/O to GND 13 V
I = 1A, TLP, GND to I/O 3 V
I = 5A, TLP, GND to I/O 6 V
VBR Break-down voltage IIO = 1mA 6.5 7.5 8.5 V
ILEAK Leakage current VIO = 2.5V 0.02 1 nA
RDYN Dynamic resistance Any I/O to GND Terminal(1) 0.8 Ω
GND to any I/O Terminal(1) 0.7 Ω
CL Line capacitance VIO = 2.5V, f = 1MHz, I/O to GND 0.45 0.55 pF
CCROSS Channel to channel input capacitance GND Terminal = 0V, f = 1MHz, VBIAS = 2.5 V,
between channel terminals		 0.003 pF
ΔCIO-TO-GND Variation of channel input capacitance GND Terminal = 0V, f = 1MHz, VBIAS = 2.5 V,
Channel_x terminal to GND – Channel_y terminal to GND		 0.05 pF
(1) Extraction of RDYN using least squares fit of TLP characteristics between I = 10A and I = 20A.

7.6 Typical Characteristics

At TA = 25°C, unless otherwise noted
D001_SLVSC54.gif
Figure 1. IEC 61000-4-2 Clamping Voltage, +8kV Contact
D003_SLVSC54.gif
Figure 3. Insertion Loss
D004_SLVSC54.gif
Figure 5. TLP, tPW = 100 nS, tRISE = 10 nS
D006_SLVSC54.gif
Figure 7. Surge Curves, IO to GND
D007_SLVSC54.gif
Figure 9. IO Terminal Capacitance vs VBIAS
D002_SLVSC54.gif
Figure 2. IEC 61000-4-2 Clamping Voltage, -8kV Contact
D009_SLVSC54.gif
Figure 4. IV Curve
D005_SLVSC54.gif
Figure 6. Leakage vs Temperature
D008_SLVSC54.gif
Figure 8. Surge Curves, GND to IO