SLVS816A July   2008  – December 2015 TPD8S009

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 IEC 61000-4-2 ESD Protection
      2. 7.3.2 IEC 61000-4-5 Surge Protection
      3. 7.3.3 I/O Capacitance
      4. 7.3.4 Low Leakage Current
      5. 7.3.5 Supports High-Speed Differential Data Rates
      6. 7.3.6 Ioff Feature
      7. 7.3.7 Industrial Temperature Range
      8. 7.3.8 Easy Straight Through Routing
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Signal Range on High Speed TMDS Pins
        2. 8.2.2.2 Bandwidth on High-Speed TMDS Pins
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The TPD8S009 is an eight-channel TVS diode array for ESD protection. TPD8S009 is rated to dissipate contact ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4), with ±8-kV contact discharge ESD protection. The low capacitance (0.8 pF) of this device, coupled with the excellent matching between differential signal pairs enables this device to provide transient voltage suppression circuit protection for high-speed idfferential data rates (3-dB bandwidth > 4 GHz).

The TPD8S009 offers an optional VCC supply pin which can be connected to system supply plane. There is a blocking diode at the VCC pin to enable the Ioff feature for the TPD8S009. The TPD8S009 can handle live signal at the signal pins when the VCC pin is connected to 0 V. The VCC pin allows all the internal circuit nodes of the TPD8S009 to be at known potential during start-up time. However, connecting the optional VCC pin to board supply plane doesn't affect the system level ESD performance of the TPD8S009.

7.2 Functional Block Diagram

TPD8S009 circuitdiagram_lvs816.gif

7.3 Feature Description

7.3.1 IEC 61000-4-2 ESD Protection

The I/O pins can withstand ESD events up to ±8-kV contact and ±9-kV air. An ESD and surge clamp diverts the current to ground.

7.3.2 IEC 61000-4-5 Surge Protection

The I/O pins can withstand surge events up to 2.5 A and 25 W (8/20-µs waveform). An ESD and surge clamp diverts this current to ground.

7.3.3 I/O Capacitance

The capacitance between each I/O pin to ground is 0.8 pF (typical). This device can support data rates up to
3.4 Gbps.

7.3.4 Low Leakage Current

The I/O pins feature a low leakage current of 10 nA (typical) with an IO bias of 3.3 V and VCC bias of 5 V.

7.3.5 Supports High-Speed Differential Data Rates

The I/O pins low capacitance of 0.8 pF (typical) gives them a typical –3-dB bandwidth > 4 GHz. This allows the TPD8S009 to protect interfaces with high-speed signals like HDMI 1.4.

7.3.6 Ioff Feature

The TPD8S009 offers an optional VCC supply pin which can be connected to system supply plane. There is a blocking diode at the VCC pin which makes it so the TPD4S009 can handle live signal at the D+, D– pins when the VCC pin is connected to 0 V. This is the Ioff feature, which is crucial for HDMI, as a live signal can be put on the IO pins when the system is powered off.

7.3.7 Industrial Temperature Range

This device features an industrial operating range of –40°C to +85°C.

7.3.8 Easy Straight Through Routing

The layout of this device makes it simple and easy to add protection to an existing layout. The packages offers flow-through routing, requiring minimal modification to an existing layout. Flow-through routing also allows the PCB designer to optimize the signal integrity of any high-speed signals being protected.

7.4 Device Functional Modes

TPD8S009 is a passive-integrated circuit that activates whenever voltages above VBR or below the lower diodes Vforward (–0.6 V) are present upon the circuit being protected. During ESD events, voltages as high as ±9 kV can be directed to ground and VCC through the internal diode network. Once the voltages on the protected lines fall below the trigger voltage of the TPD8S009 (usually within 10's of nano-seconds) the device reverts back to a high-impedance state.