JAJSO48E October   2004  – May 2022 TPIC1021

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LIN Bus Pin
        1. 8.3.1.1 Transmitter Characteristics
        2. 8.3.1.2 Receiver Characteristics
      2. 8.3.2 Transmit Input Pin (TXD)
        1. 8.3.2.1 TXD Dominant State Timeout
      3. 8.3.3 Receive Output Pin (RXD)
        1. 8.3.3.1 RXD Wake-up Request
      4. 8.3.4 Ground (GND)
      5. 8.3.5 Enable Input Pin (EN)
      6. 8.3.6 NWake Input Pin (NWake)
      7. 8.3.7 Inhibit Output Pin (INH)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating States
        1. 8.4.1.1 Normal Mode
        2. 8.4.1.2 Low Power Mode
        3. 8.4.1.3 Wake-Up Events
        4. 8.4.1.4 Standby Mode
      2. 8.4.2 Supply Voltage (VSUP)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

7.6 Timing Requirements

MINNOMMAXUNIT
D1Duty cycle 1(1)(2)THREC(max) = 0.744×VSUP, THDOM(max) = 0.581×VSUP, VSUP = 7.0 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 7-10.396
D2Duty cycle 2(1)(2)THREC(max) = 0.284×VSUP, THDOM(max) = 0.422×VSUP, VSUP = 7.6 V to 18 V, tBIT = 50 µs (20 kbps), See Figure 7-10.581
D3Duty cycle 3(1)(2)THREC(max) = 0.778×VSUP, THDOM(max) = 0.616×VSUP, VSUP = 7.0 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 7-10.417
D4Duty cycle 4(1)(2)THREC(max) = 0.251×VSUP, THDOM(max) = 0.389×VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 µs (10.4 kbps), See Figure 7-10.590
trx_pdrReceiver rising propagation delay timeRL = 2.4 kΩ, CL = 20 pF, See Figure 7-16µs
trx_pdfReceiver rising propagation delay timeRL = 2.4 kΩ, CL = 20 pF, See Figure 7-16µs
trx_symSymmetry of receiver propagation delay time (rising edge)with respect to falling edge, See Figure 7-1–22µs
tNWakeNWake filter time for local wake-upSee Figure 7-12550100µs
tLINBUSLIN wake-up filter time (dominant time for wake-up via LIN bus)See Figure 7-12550100µs
tDSTDominant state timeout(3)See Figure 7-16914ms
(1) Duty cycle = tBUS_rec(min)/ (2×tBIT)
(2) Duty Cycles: LIN Driver bus load conditions (CLINBUS, RLINBUS): Load1 = 1 nF, 1 kΩ; Load2 = 6.8 nF, 660 Ω; Load3 = 10 nF, 500 Ω. Duty Cycles 3 and 4 are defined for 10.4 kbps operation. The TPIC1021 also meets these lower speed requirements, while it is capable of the higher speed 20.0 kbps operation as specified by Duty Cycles 1 and 2. SAEJ2602 derives propagation delay equations from the LIN 2.0 duty cycle definitions (LIN 2.1 compatible), for details please refer to the SAEJ2602 specification.
(3) Dominant state timeout will limit the minimum data rate to 2.4 kbps.
GUID-8704CDB1-C99F-42A1-B621-9046AE18E57F-low.gifFigure 7-1 Definition of Bus Timing Parameters