JAJSN87A July   2022  – December 2022 TPS1HC30-Q1

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 推奨動作条件
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Accurate Current Sense
      2. 8.3.2 Programmable Current Limit
        1. 8.3.2.1 Capacitive Charging
      3. 8.3.3 Inductive-Load Switching-Off Clamp
      4. 8.3.4 Full Protections and Diagnostics
        1. 8.3.4.1  Short-Circuit and Overload Protection
        2. 8.3.4.2  Open-Load and Short-to-Battery Detection
        3. 8.3.4.3  Short-to-Battery Detection
        4. 8.3.4.4  Reverse-Polarity and Battery Protection
        5. 8.3.4.5  Latch-Off Mode
        6. 8.3.4.6  Thermal Protection Behavior
        7. 8.3.4.7  UVLO Protection
        8. 8.3.4.8  Loss of GND Protection
        9. 8.3.4.9  Loss of Power Supply Protection
        10. 8.3.4.10 Reverse Current Protection
        11. 8.3.4.11 Protection for MCU I/Os
      5. 8.3.5 Diagnostic Enable Function
    4. 8.4 Device Functional Modes
      1. 8.4.1 Working Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Dynamically Changing Current Limit
        2. 9.2.2.2 EMC Transient Disturbances Test
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
        1. 9.4.2.1 Without a GND Network
        2. 9.4.2.2 With a GND Network
      3. 9.4.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Inductive-Load Switching-Off Clamp

When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance characteristics. The power FET can break down if the voltage is not clamped during the current-decay period. To protect the power FET in this situation, internally clamp the drain-to-source voltage, namely VDS,clamp, the clamp diode between the drain and gate.

Equation 6. GUID-DA5AD4C2-79B5-4AF5-ADE3-2D3C0CF9E8E2-low.gif

During the current-decay period (TDECAY), the power FET is turned on for inductance-energy dissipation. Both the energy of the power supply (EBAT) and the load (ELOAD) are dissipated on the high side power switch itself, which is called EHSD. If resistance is in series with inductance, some of the load energy is dissipated in the resistance.

Equation 7. GUID-CE5858CC-BBAE-450D-A25D-3FA661B39518-low.gif

From the high side power switch view, EHSD equals the integration value during the current-decay period.

Equation 8. GUID-81B6C51D-9DCC-4C64-9D9F-E371B7E476C8-low.gif
Equation 9. GUID-C0872E71-3548-4596-9AAB-015C6D17416B-low.gif
Equation 10. GUID-F409810F-64DA-4A0F-BC80-591F81A85800-low.gif

When R approximately equals 0, EHSD can be given simply as:

Equation 11. GUID-65A608B2-75E0-49EE-9768-58F013DEAEB5-low.gif
GUID-F18D3751-3D5D-4E32-932F-6F2F31597D98-low.gifFigure 8-10 Driving Inductive Load
GUID-E7B1E050-6D96-474F-B275-AD862C6914BA-low.gifFigure 8-11 Inductive-Load Switching-Off Diagram

As discussed previously, when switching off, battery energy and load energy are dissipated on the high side power switch, which leads to the large thermal variation. For each high side power switch, the upper limit of the maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test condition: VVS = 13.5 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2- × 70-μm copper, 2- × 35-μm copper, thermal pad copper area 600 mm2.