JAJSHI3C March 2019 – October 2019 TPS23881
COMMAND = 02h with 1 Data Byte, Read only
COMMAND = 03h with 1 Data Byte, Clear on Read
Active high, each bit corresponds to a particular event that occurred.
Each bit xxx1-4 represents an individual channel.
A read at each location (02h or 03h) returns the same register data with the exception that the Clear on Read command clears all bits of the register.
If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.
Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.
|LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset|
|7–4||PGC4–PGC1||R or CR||0||Indicates that a power good status change occurred.
1 = Power good status change occurred
0 = No power good status change occurred
|3–0||PEC4–PEC1||R or CR||0||Indicates that a power enable status change occurred.
1 = Power enable status change occurred
0 = No power enable status change occurred
For 4-pair wired Ports, the PECn bits will be updated individually as status changes for each channel.
For 4-Pair Single Signature devices, the PGCn bits will be set only after the status has changed on both channels. This is done to prevent the possible scenario of dual interrupts as the second Channel completes processing shortly after the first.
For 4-Pair Dual Signature devices, the PECn and PGCn bits will be set as the status changes on each channel.