JAJSHI3C March 2019 – October 2019 TPS23881
COMMAND = 06h with 1 Data Byte, Read only
COMMAND = 07h with 1 Data Byte, Clear on Read
Active high, each bit corresponds to a particular event that occurred.
Each bit xxx1-4 represents an individual channel.
A read at each location (06h or 07h) returns the same register data with the exception that the Clear on Read command clears all bits of the register. These bits are cleared when channel-n is turned off.
If this register is causing the INT pin to be activated, this Clear on Read will release the INT pin.
Any active bit will have an impact on the Interrupt register as indicated in the Interrupt register description.
|LEGEND: R/W = Read/Write; R = Read only; ; CR = Clear on Read, -n = value after reset|
|7–4||DISF4–DISF1||R or CR||0||Indicates that a disconnect event occurred.
1 = Disconnect event occurred
0 = No disconnect event occurred
|3–0||PCUT4–PCUT1||R or CR||0||Indicates that a tOVLD Fault occurred.
1 = tOVLD Fault occurred
0 = No tOVLD Fault occurred
For 4-pair wired ports, the DISFn and PCUTn bits will be updated individually as status changes for each channel.
Disconnect events for 4-Pair single signature devices will set both corresponding bits, whereas 4-pair dual signature devices will have independent disconnect events per channel.
In the event a singular channel of a 4-pair dual signature device is turned off due to a Disconnect or 2-Pair PCut fault, power may be reapplied to that channel by setting the PWON bit in 0x19h provided the detection and classification are still valid and the Power Allocation settings in 0x29 are sufficient based on the assigned classification of the powered channel.
If PCUT is disabled for a channel, this channel will not be automatically turned off during a PCUT fault condition. However, the PCUT fault flag will still be operational, with a fault timeout equal to tOVLD.
Clearing a PCUT event has no impact on the TLIM or TOVLD counters.