JAJSHI3C March 2019 – October 2019 TPS23881
COMMAND = 1Ah with 1 Data Byte, Write Only
Push button register.
Writing a 1 at a bit location triggers an event while a 0 has no impact. Self-clearing bits.
|LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset|
|7||CLRAIN||W||0||Clear all interrupts bit. Writing a 1 to CLRAIN clears all event registers and all bits in the Interrupt register. It also releases the INT pin|
|6||CLINP||W||0||When set, it releases the INT pin without any impact on the Event registers nor on the Interrupt register.|
|4||RESAL||W||0||Reset all bits when RESAL is set. Results in a state similar to a power-up reset. Note that the VDUV and VPUV bits (Supply Event register) follow the state of VDD and VPWR supply rails.|
|3–0||RESP4–RESP1||W||0||Reset channel bits. Used to force an immediate channel(s) turn off in any mode, by writing a 1 at the corresponding RESPn bit location(s).
Note: For a 4-pair wired port, setting a RESPn bit for either channel will result in both channels being reset.
Setting the RESAL bit will result in all of the I2C register being restored to the RST condition with the exception of those in the following table:
|0x00||All||Pre RESAL value will remain|
|0x0A/B||TSD, VPUV, VDWRN, and VPUV|
|0x2C and 0x2E||All|
Setting the RESAL bit for only one group of four channels (1-4 or 5-8) will result in only those four channels being reset.
After using the CLINP command, the INT pin will not be reasserted for any interrupts until all existing interrupts have been cleared.
Setting the RESPn bit will immediate turn off the associated channel and clear the registers according to the following table:
|Register||Bits to be Reset|
|0x04||CLSCn and DETCn|
|0x06||DISFn and PCUTn|
|0x08||STRTn and ILIMn|
|0x0C-0F||Requested Class and Detection|
|0x10||PGn and PEn|
|0x14||CLEn and DETEn|
|0x1C||ACn and CCnn|
|0x1E-21||2P Policing set to 0xFFh|
|0x2A-2B||4P Policing set to 0xFFh|
|0x2D||NLMnn, NCTnn, 4PPCTnn, and DCDTnn|
|0x30-3F||Channel Voltage and Current Measurements|
|0x44 - 47||Detection Resistance Measurements|
|0x4C-4F||Assigned Class and Previous Class|
Only the bits associated with the channel/port ("n") with RESPn set will be cleared. Those bits associated with channels/ports remaining in operation will not be changed.
it may take upwards of 5 ms before all of the registers are cleared following a RESPn command.
The RESPn command will cancel any ongoing cool down cycles .
Users need to wait at least 3ms before trying to reenable discovery or power on ports following a RESPn command.