JAJSGA2F September   2018  – June 2021 TPS2663

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. 9.3.1.1 Thermal Regulation Loop
      2. 9.3.2  PGOOD and PGTH
        1. 9.3.2.1 PGTH as VOUT Sensing Input
      3. 9.3.3  Undervoltage Lockout (UVLO)
      4. 9.3.4  Overvoltage Protection (OVP)
      5. 9.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 9.3.6  Reverse Current Protection
      7. 9.3.7  Overload and Short Circuit Protection
        1. 9.3.7.1 Overload Protection
          1. 9.3.7.1.1 Active Current Limiting at 1x IOL, (TPS26630 and TPS26632 Only)
          2. 9.3.7.1.2 Active Current Limiting with 2x IOL Pulse Current Support, (TPS26631, TPS26633, TPS26635 and TPS26636 Only)
        2. 9.3.7.2 Short Circuit Protection
          1. 9.3.7.2.1 Start-Up With Short-Circuit On Output
      8. 9.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635 and TPS26636 Only)
      9. 9.3.9  Current Monitoring Output (IMON)
      10. 9.3.10 FAULT Response ( FLT)
      11. 9.3.11 IN_SYS, IN, OUT and GND Pins
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Power Path Protection in a PLC System
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Output Buffer Capacitor – COUT
        4. 10.2.2.4 PGTH Set Point
        5. 10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 10.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 10.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
      2. 10.3.2 Priority Power MUX Operation
      3. 10.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 10.4 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
  • PWP|20
サーマルパッド・メカニカル・データ

12.1 Layout Guidelines

  • For all the applications, a 0.1 µF or higher value ceramic decoupling capacitor is recommended between IN_SYS terminal and GND.
  • The external FET Q1 should be placed with DRAIN close to the VIN pins of the IC and connected through a plane. The fast pull down switch Q2 DRAIN and SOURCE should be placed very close to the GATE and SOURCE terminals of Q1 with very short loop. See Figure 12-1 and Figure 12-2 for a typical PCB layout example.
  • The optimum placement of decoupling capacitor is closest to the IN_SYS and GND terminals of the device. Care must be taken to minimize the loop area formed by the bypass-capacitor connection, the IN_SYS terminal, and the GND terminal of the IC.
  • High current carrying power path connections must be as short as possible and must be sized to carry at least twice the full-load current.
  • Locate all the TPS2663x family support components R(ILIM), C(dVdT), R(IMON), UVLO, OVP and PGTH resistors close to their connection pin. Connect the other end of the component to the GND with shortest trace length.
  • The trace routing for the RILIM component to the device must be as short as possible to reduce parasitic effects on the current limit and current monitoring accuracy. These traces must not have any coupling to switching signals on the board.
  • Protection devices such as TVS, snubbers, capacitors, or diodes must be placed physically close to the device they are intended to protect, and routed with short traces to reduce inductance. For example, a protection Schottky diode is recommended to address negative transients due to switching of inductive loads, and it must be physically close to the OUT and GND pins.
  • Thermal Considerations: When properly mounted, the PowerPAD package provides significantly greater cooling ability. To operate at rated power, the PowerPAD must be soldered directly to the board GND plane directly under the device. Other planes, such as the bottom side of the circuit board can be used to increase heat sinking in higher current applications.