JAJSGA2F September   2018  – June 2021 TPS2663

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. 9.3.1.1 Thermal Regulation Loop
      2. 9.3.2  PGOOD and PGTH
        1. 9.3.2.1 PGTH as VOUT Sensing Input
      3. 9.3.3  Undervoltage Lockout (UVLO)
      4. 9.3.4  Overvoltage Protection (OVP)
      5. 9.3.5  Input Reverse Polarity Protection (B_GATE, DRV)
      6. 9.3.6  Reverse Current Protection
      7. 9.3.7  Overload and Short Circuit Protection
        1. 9.3.7.1 Overload Protection
          1. 9.3.7.1.1 Active Current Limiting at 1x IOL, (TPS26630 and TPS26632 Only)
          2. 9.3.7.1.2 Active Current Limiting with 2x IOL Pulse Current Support, (TPS26631, TPS26633, TPS26635 and TPS26636 Only)
        2. 9.3.7.2 Short Circuit Protection
          1. 9.3.7.2.1 Start-Up With Short-Circuit On Output
      8. 9.3.8  Output Power Limiting, PLIM (TPS26632, TPS26633, TPS26635 and TPS26636 Only)
      9. 9.3.9  Current Monitoring Output (IMON)
      10. 9.3.10 FAULT Response ( FLT)
      11. 9.3.11 IN_SYS, IN, OUT and GND Pins
      12. 9.3.12 Thermal Shutdown
      13. 9.3.13 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Power Path Protection in a PLC System
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Current-Limit Threshold—R(ILIM) Selection
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Output Buffer Capacitor – COUT
        4. 10.2.2.4 PGTH Set Point
        5. 10.2.2.5 Setting Output Voltage Ramp Time—(tdVdT)
          1. 10.2.2.5.1 Support Component Selections— RPGOOD and C(IN)
        6. 10.2.2.6 Selecting Q1, Q2 and TVS Clamp for Surge Protection
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
      2. 10.3.2 Priority Power MUX Operation
      3. 10.3.3 Input Protection for a Compact 24-V Auxiliary Power Supply for Servo Drives
    4. 10.4 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • RGE|24
  • PWP|20
サーマルパッド・メカニカル・データ

Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN_SYS) = V(IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD =  FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
UVLO INPUT (UVLO)
UVLO_ton(dly)UVLO switch turnon delayUVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV with V(PGTH  < V(PGTHF), C(dVdT) ≥ 10 nF,  [C(dVdT) in nF]742 + 49.5 x C(dVdT)µs
UVLO_ton(fast_dly)UVLO switch turnon delay (fast)UVLO↑  (100 mV above V(UVLOR)) to FET ON with V(PGTH) > V(PGTHF)70150251µs
UVLO_toff(dly)UVLO switch turnoff delayUVLO↓(20 mV below V(UVLOF)) to FLT91116µs
tUVLO_FLTdly)UVLO to fault de-assertion delayUVLO↑  to FLT ↑ delay500617700µs
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP_tOFF(dly)OVP switch turnoff delayOVP↑ (20 mV above V(OVPR)) to FLT8.51114µs
OVP_ton(fast_dly)OVP switch turnon delay (fast)OVP↓ (100 mV below V(OVPF)) to FET ON with V(PGTH ) > V(PGTHF)58129225µs
OVP_ton(dly)OVP switch disable delayOVP↓ (100 mV below V(OVPF)) to FET ON with V(PGTH ) < V(PGTHF), C(dVdT) ≥ 10 nF,  [C(dVdT) in nF]150 + 49.5 x C(dVdT)µs
tOVC(dly)Maximum duration in over voltage clamp operationTPS26632, TPS26633,TPS26635 and TPS26636 Only162ms
OVC_tFLT(dly)FLT assertion delay in over voltage clamp operationTPS26632, TPS26633,TPS26635 and TPS26636 Only617µs
SHUTDOWN CONTROL INPUT ( SHDN)
tSD(dly)SHUTDOWN entry delaySHDN↓ (below V(SHUTF)) to FET OFF0.811.5µs
CURRENT LIMIT
tFASTTRIP(dly)Hot-short response timeI(OUT) > I(SCP)1µs
Soft short responseI(FASTTRIP) < I(OUT) < I(SCP)2.23.24.5µs
tCL_PLIM(dly)Maximum duration in current & (power limiting: TPS26632, TPS26633, TPS26635 and TPS26636 Only)129162202ms
tCB(dly)Maximum duration in 2x current limiting I(OL) < I(OUT) ≤ I(2xOL)2025.531ms
tCBRetry(dly)Retry delay in Pulse over current limitingMODE = GND, TPS26631, TPS26633,TPS26635 and TPS26636 Only550670800ms
tCL_PLIM_FLT(dly)FLT delay in current & (power limiting: TPS26632, TPS26633, TPS26635 and TPS26636 Only)1.091.31.6ms
REVERSE CURRENT BLOCKING (RCB) COMPARATOR
tRCB(fast_dly)Reverse protection comparator dectection delay (reverse)(V(IN_SYS) – V(OUT))↓ (1 V overdrive below V(REVTH)) to V(DRV) – V(IN_SYS) = V(DRV_OH)0.170.37µs
tRCB(dly)(V(IN_SYS) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to V(DRV) – V(IN_SYS) = V(DRV_OH)0.483µs
tRCB(flt_dly)Fault assertion Delay(V(IN_SYS) – V(OUT))↓ (10 mV overdrive below V(REVTH)) to FLT500617800µs
tFWD_FLT(dly)Reverse protection comparator dectection delay (forward)(V(IN_SYS) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to V(BGATE) – V(IN_SYS) = 5 V, C(BFET-IN_SYS) = 4.7 nF0.87ms
Fault de-assertion Delay(V(IN_SYS) – V(OUT))↑ (10 mV overdrive above V(FWDTH)) to FLT434605800µs
OUTPUT RAMP CONTROL (dVdT)
t(FASTCHARGE)Output ramp time in fast chargingC(dVdT) = Open, 10% to 90% V(OUT), C(OUT) = 1 µF; V(IN) = 24V350495700µs
t(dVdT)Output ramp timeC(dVdT) = 22 nF, 10% to 90% V(OUT), V(IN) = 24V8.35ms
POWER GOOD (PGOOD)
tPGOODRPGOOD delay (deglitch) timeRising edge1.071.31.6ms
tPGOODFPGOOD delay (deglitch) timeFalling edge, PGTH↓ (10mV below V(PGTHF))1.32.124µs
FAULT FLAG ( FLT)
tCB_FLT(dly)FLT assertion delay in Pulse over current limitingDelay from I(OUT) > I(OL) to FLT↓. TPS26631, TPS26633, TPS26635 and TPS26636 Only2225.530ms
THERMAL PROTECTION
t(TSD_retry)Retry delay in TSDMODE = GND500648800ms
t(Treg_timeout)Thermal Regulation Timeout2.32.542.9s