JAJSLC2C march   2014  – march 2021 TPS3700-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inputs (INA+, INB–)
      2. 7.3.2 Outputs (OUTA, OUTB)
      3. 7.3.3 Window Voltage Detector
      4. 7.3.4 Immunity to Input Terminal Voltage Transients
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VPULLUP to a Voltage Other Than VDD
      2. 8.1.2 Monitoring VDD
      3. 8.1.3 Monitoring a Voltage Other Than VDD
      4. 8.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Supply Capacitor
        2. 8.2.1.2 Input Capacitors
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-C15EE746-D510-4C3E-9605-30BFAF92EFD3-low.gif Figure 5-1 DDC Package 
SOT-6
Top View
GUID-B4A43690-3AE6-4E3A-89A0-26661D2CCAE2-low.gif Figure 5-2 DSE Package
WSON-6
Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME DDC DSE
GND 2 5 — Ground
INA+ 3 4 I This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal drops below the threshold voltage (VIT+ – VHYS), OUTA is driven low.
INB– 4 3 I This pin is connected to the voltage to be monitored with the use of an external resistor divider. When the voltage at this terminal exceeds the threshold voltage (VIT+), OUTB is driven low.
OUTA 1 6 O INA+ comparator open-drain output. OUTA is driven low when the voltage at this comparator is below (VIT+ – VHYS). The output goes high when the sense voltage returns above the respective threshold (VIT+).
OUTB 6 1 O INB– comparator open-drain output. OUTB is driven low when the voltage at this comparator exceeds VIT+. The output goes high when the sense voltage returns below the respective threshold (VIT+ – VHYS).
VDD 5 2 I Supply voltage input. Connect a 1.8-V to 18-V supply to VDD to power the device. Good analog design practice is to place a 0.1-µF ceramic capacitor close to this pin.