JAJSLC2C march   2014  – march 2021 TPS3700-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Inputs (INA+, INB–)
      2. 7.3.2 Outputs (OUTA, OUTB)
      3. 7.3.3 Window Voltage Detector
      4. 7.3.4 Immunity to Input Terminal Voltage Transients
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 VPULLUP to a Voltage Other Than VDD
      2. 8.1.2 Monitoring VDD
      3. 8.1.3 Monitoring a Voltage Other Than VDD
      4. 8.1.4 Monitoring Overvoltage and Undervoltage for Separate Rails
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Input Supply Capacitor
        2. 8.2.1.2 Input Capacitors
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Trademarks
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Outputs (OUTA, OUTB)

In a typical TPS3700-Q1 application, the outputs are connected to a reset or enable input of the processor (such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-specific integrated circuit [ASIC]) or the outputs are connected to the enable input of a voltage regulator (such as a DC-DC or low-dropout regulator [LDO]).

The TPS3700-Q1 device provides two open-drain outputs (OUTA and OUTB). Pullup resistors must be used to hold these lines high when the output goes to high impedance (not asserted). By connecting pullup resistors to the proper voltage rails, the outputs can be connected to other devices at the correct interface-voltage levels. The TPS3700-Q1 outputs can be pulled up to 18 V, independent of the device supply voltage. To ensure proper voltage levels, some thought should be given while choosing the pullup resistor values. The pullup resistor value is determined by VOL, sink-current capability, and output-leakage current (Ilkg(OD)). These values are specified in the Section 6.5 table. By using wired-AND logic, OUTA and OUTB can merge into one logic signal.

Table 7-1 and the Section 7.3.1 section describe how the outputs are asserted or de-asserted. See Figure 6-1 for a timing diagram that describes the relationship between threshold voltages and the respective output.