The TPS3836, TPS3837, and TPS3838 device families of supervisory circuits provide circuit initialization and timing supervision, primarily for digital signal processors (DSP) and processor-based systems.
During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps the RESET output active as long as VDD remains below the threshold voltage of VIT. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time starts after VDDrises above the threshold voltage VIT.
When CT is connected to GND, a fixed delay time of typically 10 ms is asserted. When connected to VDD, the delay time is typically 200 ms. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider.
The TPS3836 has an active-low, push-pull RESET output. The TPS3837 has an active-high, push-pull RESET, and the TPS3838 integrates an active-low, open-drain RESET output. The product spectrum is designed for supply voltages of 1.8 V, 2.5 V, 3.0 V, and 3.3 V. The circuits are available in either a SOT23-5 or a 2-mm × 2-mm SON-6 package. The TPS3836, TPS3837, and TPS3838 families are characterized for operation over a temperature range of –40°C to 85°C.
|PART NUMBER||PACKAGE||BODY SIZE (NOM)|
|TPS383x||WSON (6)||2.00 mm × 2.00 mm|
|SOT (5)||2.90 mm × 1.60 mm|