JAJSIJ2C September   2020  – January 2024 TPS3899

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison
  6.   Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD Hysteresis
      2. 6.3.2 User-Programmable Sense and Reset Time Delay
      3. 6.3.3 RESET/RESET Output
      4. 6.3.4 SENSE Input
        1. 6.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation (VDD > VDD(min))
      2. 6.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 6.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 Layout Guidelines
        2. 7.2.5.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

CTR = CTS = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load (CLOAD) = 10 pF and over the operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VDD Input supply voltage (Open Drain Low and Push Pull Low) 0.85 6 V
VDD Input supply voltage (Push Pull High) 1 6 V
VIT– (1) Negative-going input threshold range for all output configs 0.8 5.4 V
VADJ-VIT– Negative-going input threshold for adjustable sense threshold version 0.505 V
VIT– accuracy Negative-going input threshold accuracy VIT– = 0.505 V (ADJ version) or 0.8 V to 1.7 V (Fixed threshold) –2.5 ±0.5 2.5 %
VIT– = 1.8 V to 5.4 V (Fixed threshold) –2 ±0.5 2
VHYS Hysteresis on VIT– VIT– = 0.505 V and 0.8 V 3 5 8 %
VIT– = 0.9 V to 5.4 V 3 5 7 %
ISENSE Current into Sense pin, fixed threshold version VDD = VSENSE = 6 V
 0.025 0.1 µA
Current into Sense pin, ADJ version VDD = VSENSE = 6 V
 0.025 0.05 µA
IDD Supply current into VDD pin when sense pin is separate VDD = VSENSE = 6 V
VIT– = 0.505 V and 0.8 V to 5.4 V		 0.125 1 µA
VTH_CTS Voltage threshold to stop CTS capacitor charge and assert RESET 0.73 * VDD V
VTH_CTR Voltage threshold to stop CTR capacitor charge and deassert RESET 0.73 * VDD V
RCTS CTS pin internal pull up resistance 500 kΩ
RCTR CTR pin internal pull up resistance 500 kΩ
TPS3899DL (Open-drain active-low)
VPOR Power on reset voltage (2) VOL(max) = 300 mV
I RESET(Sink) = 15 µA		 700 mV
VOL Low level output voltage
 		 VDD = 0.85 V 
I RESET(Sink) = 15 µA		 300 mV
VDD = 3.3 V
I RESET(Sink) = 2 mA		 300 mV
Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 6 V, TA = –40℃ to 85℃ 10 100 nA
VDD = VPULLUP = 6 V 10 350 nA
TPS3899PL (Push-pull active-low)
VPOR Power on reset voltage (2) VOL(max) = 300 mV
I RESET(Sink) = 15 µA		 700 mV
VOL Low level output voltage
 		 VDD = 0.85 V 
I RESET(Sink) = 15 µA		 300 mV
VDD = 3.3 V
I RESET(Sink) = 2 mA		 300 mV
VOH High level output voltage
 		 VDD = 1.8 V
I RESET(Source) = 500 µA		 0.8VDD V
VDD = 3.3 V
I RESET(Source) = 500 µA		 0.8VDD V
VDD = 6 V
I RESET(Source) = 2 mA		 0.8VDD V
TPS3899PH (Push-pull active-high)
VPOR Power on reset voltage(2) VOH(min) = 0.8VDD
IRESET (Source) = 15 uA		 900 mV
VOL Low level output voltage
 		 VDD = 3.3 V
IRESET(Sink) = 500 µA		 300 mV
VDD = 6 V
IRESET(Sink) = 2 mA		 300 mV
VOH High level output voltage
 		 VDD = 1V 
IRESET(Sink) = 15 µA		 0.8VDD V
VDD = 1.5 V
IRESET(Sink) = 500 µA		 0.8VDD V
VDD = 3.3 V
IRESET(Sink) = 2 mA		 0.8VDD V
(1) VIT- threshold voltage range from 0.8 V to 5.4 V (for DL, PL) and 1 to 5.4 V (for PH) in 100 mV steps, for released versions see Device Voltage Thresholds table.
(2) Minimum VDD voltage level for a controlled output state. Below VPOR, the output cannot be determined.