SLVS861F August   2008  – June 2020 TPS40210-Q1 , TPS40211-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum On-Time and Off-Time Considerations
      2. 7.3.2  Current Sense and Overcurrent
      3. 7.3.3  Current Sense and Subharmonic Instability
      4. 7.3.4  Current Sense Filtering
      5. 7.3.5  Soft Start
      6. 7.3.6  BP Regulator
      7. 7.3.7  Shutdown (DIS/EN Pin)
      8. 7.3.8  Control Loop Considerations
      9. 7.3.9  Gate Drive Circuit
      10. 7.3.10 TPS40211-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Setting the Oscillator Frequency
      2. 7.4.2 Synchronizing the Oscillator
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Duty Cycle Estimation
        2.  Inductor Selection
        3.  Rectifier Diode Selection
        4.  Output Capacitor Selection
        5.  Input Capacitor Selection
        6.  Current Sense and Current Limit
        7.  Current Sense Filter
        8.  Switching MOSFET Selection
        9.  Feedback Divider Resistors
        10. Error Amplifier Compensation
        11. R-C Oscillator
        12. Soft-Start Capacitor
        13. Regulator Bypass
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



Pin Configuration and Functions

DGQ Package
10-Pin PDSO PowerPAD™ Package
(Top View)
TPS40210-Q1 TPS40211-Q1 pinout_dgq_SLVS861.gif

Pin Functions

BP 9 O Regulator output. Connect a 1-μF bypass capacitor from this pin to GND.
COMP 4 O Error amplifier output. Connect a control-loop compensation network between the COMP pin and the FB pin.
DIS/EN 3 I Disable or enable. Pulling this pin high places the part into a shutdown mode. The prime characteristic of shutdown mode is a very low quiescent current. Shutdown mode disables the functionality of all blocks and shuts down the BP regulator. This pin has an internal 1-MΩ pulldown resistor to GND. Leaving this pin unconnected enables the device.
FB 5 I Error amplifier inverting input. Connect a voltage divider from the output to this pin to set the output voltage. Connect a compensation network between this pin and COMP.
GDRV 8 O Connect the gate of the power N-channel MOSFET to this pin.
GND 6 Device ground
ISNS 7 I Current sense. Connect an external current-sensing resistor between this pin and GND. The voltage on this pin provides current feedback in the control loop for detecting an overcurrent condition. Declaration of an overcurrent condition occurs when ISNS pin voltage exceeds the overcurrent threshold voltage, 150 mV typical.
RC 1 I Switching-frequency setting. Connect a capacitor from the RC pin to GND. Connect a resistor from the RC pin to VDD of the IC power supply and a capacitor from RC to GND.
SS 2 I Soft-start time programming. Connect a capacitor from the SS pin to GND to program the converter soft-start time. This pin also functions as a time-out timer when the power supply is in an overcurrent condition.
VDD 10 I System input voltage. Connect a local bypass capacitor from this pin to GND. Depending on the amount of required slope compensation, connection of this pin to the converter output might be desirable. See the Application and Implementation section for additional details.