SLVS861F August   2008  – June 2020 TPS40210-Q1 , TPS40211-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum On-Time and Off-Time Considerations
      2. 7.3.2  Current Sense and Overcurrent
      3. 7.3.3  Current Sense and Subharmonic Instability
      4. 7.3.4  Current Sense Filtering
      5. 7.3.5  Soft Start
      6. 7.3.6  BP Regulator
      7. 7.3.7  Shutdown (DIS/EN Pin)
      8. 7.3.8  Control Loop Considerations
      9. 7.3.9  Gate Drive Circuit
      10. 7.3.10 TPS40211-Q1
    4. 7.4 Device Functional Modes
      1. 7.4.1 Setting the Oscillator Frequency
      2. 7.4.2 Synchronizing the Oscillator
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Duty Cycle Estimation
        2.  Inductor Selection
        3.  Rectifier Diode Selection
        4.  Output Capacitor Selection
        5.  Input Capacitor Selection
        6.  Current Sense and Current Limit
        7.  Current Sense Filter
        8.  Switching MOSFET Selection
        9.  Feedback Divider Resistors
        10. Error Amplifier Compensation
        11. R-C Oscillator
        12. Soft-Start Capacitor
        13. Regulator Bypass
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



Soft Start

The soft-start feature of the TPS40210-Q1 and TPS40211-Q1 devices is a closed-loop soft start, meaning that the output voltage follows a linear ramp that is proportional to the ramp generated at the SS pin. This ramp is generated by an internal resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to GND. The SS pin voltage (VSS) is level shifted down by approximately VSS(ofst) (approximately 1 V) and sent to one of the + inputs (the + input with the lowest voltage dominates) of the error amplifier. When this level-shifted voltage (VSSE) starts to rise at time t1 (see Figure 22), the output voltage that the controller expects rises as well. Since VSSE starts at near 0 V, the controller attempts to regulate the output voltage from a starting point of zero volts. It cannot do this, due to the converter architecture. The output voltage starts from the input voltage less the drop across the diode (VIN – VD) and rises from there. The point at which the output voltage starts to rise (t2) is when the VSSE ramp passes the point where it is commanding more output voltage than (VIN – VD). This voltage level is labeled VSSE(1). The time required for the output voltage to ramp from a theoretical zero to the final regulated value (from t1 to t3) is determined by the time it takes for the capacitor connected to the SS pin (CSS) to rise through a 700-mV range, beginning at VSS(ofst) above GND.

TPS40210-Q1 TPS40211-Q1 vss_lus722.gifFigure 22. SS Pin Voltage and Output Voltage
TPS40210-Q1 TPS40211-Q1 v07121_SLVS861.gifFigure 23. SS Pin Functional Circuit

The required capacitance for a given soft-start time, t3 – t1 in Figure 22, is calculated in Equation 12.

Equation 12. TPS40210-Q1 TPS40211-Q1 q_tss01_lus772.gif


  • tSS is the soft-start time
  • RSS(chg) is the SS charging resistance in Ω, typically 500 kΩ
  • CSS is the value of the capacitor on the SS pin, in F
  • VBP is the value of the voltage on the BP pin in V
  • VSS(ofst) is the approximate level shift from the SS pin to the error amplifier (~1 V)
  • VFB is the error amplifier reference voltage, 700 mV typical

Note that tSS is the time it takes for the output voltage to rise from 0 V to the final output voltage. Also note the tolerance on RSS(chg) given in the Electrical Characteristics. This contributes to some variability in the output voltage rise time, and margin must be applied to account for it in design.

Also take note of VBP. Its value varies depending on input conditions. For example, a converter operating from a slowly rising input initializes VBP at a fairly low value and increases during the entire start-up sequence. If the controller has a voltage above 8 V at the input and the DIS pin is used to stop and then restart the converter, VBP is approximately 8 V for the entire start-up sequence. The higher the voltage on BP, the shorter the start-up time is and conversely, the lower the voltage on BP, the longer the start-up time is.

The soft-start time (tSS) must be chosen long enough so that the converter can start up without going into an overcurrent state. Since the overcurrent state is triggered by sensing the peak voltage on the ISNS pin, that voltage must be kept below the overcurrent threshold voltage, VISNS(oc). The voltage on the ISNS pin is a function of the load current of the converter, the rate of rise of the output voltage and the output capacitance, and the current sensing resistor. The total output current that must be supported by the converter is the sum of the charging current required by the output capacitor and any external load that must be supplied during start-up. This current must be less than the IOUT(oc) value used in Equation 5 or Equation 6 (depending on the operating mode of the converter) to determine the current sense resistor value.

In these equations, the actual input voltage at the time that the controller reaches the final output voltage is the important input voltage to use in the calculations. If the input voltage is slowly rising and is at less than the nominal input voltage when the startup time ends, the output current limit is less than IOUT(oc) at the nominal input voltage. The output capacitor charging current must be reduced (decrease COUT or increase the tSS) or IOUT(oc) must be increased and a new value for RISNS calculated.

Equation 13. TPS40210-Q1 TPS40211-Q1 q_icchg_lus772.gif
Equation 14. TPS40210-Q1 TPS40211-Q1 q_tss02_lus772.gif


  • IC(chg) is the output capacitor charging current in A
  • COUT is the total output capacitance in F
  • VOUT is the output voltage in V
  • tSS is the soft-start time from Equation 12
  • IOUT(oc) is the desired over current trip point in A
  • IEXT is any external load current in A

The capacitor on the SS pin (CSS) also plays a role in overcurrent functionality. It is used as the timer between restart attempts. The SS pin is connected to GND through a resistor, RSS(dchg), when the controller senses an overcurrent condition. Switching stops and nothing else happens until the SS pin discharges to the soft-start reset threshold, VSS(rst). At this point, the SS pin capacitor is allowed to charge again through the charging resistor RSS(chg), and the controller restarts from that point. The shortest time between restart attempts occurs when the SS pin discharges from VSS(ofst) (approximately 1 V) to VSS(rst) (150 mV) and then back to VSS(ofst) and switching resumes. In actuality, this is a conservative estimate since switching does not resume until the VSSE ramp rises to a point where it is commanding more output voltage than exists at the output of the controller. This occurs at some SS pin voltage greater than VSS(ofst) and depends on the voltage that remains on the output overvoltage the converter while switching has been halted. The fastest restart time can be calculated by using Equation 15, Equation 16, and Equation 17.

Equation 15. TPS40210-Q1 TPS40211-Q1 q_tdchg_lus772.gif
Equation 16. TPS40210-Q1 TPS40211-Q1 q_tchg_lus772.gif
Equation 17. TPS40210-Q1 TPS40211-Q1 q_trstrt_lus772.gif
TPS40210-Q1 TPS40211-Q1 vss_oc_lus772.gifFigure 24. Soft Start During Overcurrent