JAJSJT8C May   2020  – June 2021 TPS543620

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN Pins and VIN UVLO
      2. 7.3.2  Enable and Adjustable UVLO
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Switching Frequency Selection
      5. 7.3.5  Switching Frequency Synchronization to an External Clock
        1. 7.3.5.1 Internal PWM Oscillator Frequency
        2. 7.3.5.2 Loss of Synchronization
        3. 7.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 7.3.6  Ramp Amplitude Selection
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Mode Pin
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Current Protection
        1. 7.3.10.1 Positive Inductor Current Protection
        2. 7.3.10.2 Negative Inductor Current Protection
      11. 7.3.11 Output Overvoltage and Undervoltage Protection
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Output Voltage Discharge
      14. 7.3.14 Low-Side MOSFET Resistance Scaling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Discontinuous Conduction Mode during Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.0-V Output, 1-MHz Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Input Capacitor
          5. 8.2.1.2.5  Adjustable Undervoltage Lockout
          6. 8.2.1.2.6  Output Voltage Resistors Selection
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  BP5 Capacitor Selection
          9. 8.2.1.2.9  PGOOD Pullup Resistor
          10. 8.2.1.2.10 Current Limit Selection
          11. 8.2.1.2.11 Soft-Start Time Selection
          12. 8.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 8.2.1.2.13 MODE Pin
        3. 8.2.1.3 Application Curves
      2. 8.2.2 1.0-V Output, 1.5-MHz Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 3.3-V Output, 1.0-MHz Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 1.8-V Output, 1.0-MHz Typical Application
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
      5. 8.2.5 5.0-V Output, 1.0-MHz Typical Application
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
8.2.1.2.4 Input Capacitor

Input decoupling ceramic capacitors type X5R, X7R, or similar from VIN to PGND that are placed as close as possible to the IC are required. A total of at least 10 µF of capacitance is required and some applications can require a bulk capacitance. At least 1 µF of bypass capacitance is recommended as close as possible to each VIN pin to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor must be placed as close as possible to both VIN pins 8 and 12 on the same side of the board of the device to provide high frequency bypass to reduce the high frequency overshoot and undershoot on VIN and SW pins. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum RMS input current. The RMS input current can be calculated using Equation 16.

For this example design, a ceramic capacitor with at least a 16-V voltage rating is required to support the maximum input voltage. Two 10-µF, 0805, X7S, 25-V and two 0.1-μF, 0402, X7R 50-V capacitors in parallel have been selected to be placed on both sides of the IC near both VIN pins to PGND pins. Based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 5.4 µF at the nominal input voltage of 12 V. A 100-µF bulk capacitance is also used to bypass long leads when connected a lab bench top power supply.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 17. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using the nominal design example values of Ioutmax = 6 A, CIN = 5.4 μF, and fSW = 1000 kHz, the input voltage ripple with the 12 V nominal input is 85 mV and the RMS input ripple current with the 4.5 V minimum input is 4.9 A.

Equation 16. GUID-76F9A5AE-9FE0-4C6F-8C67-E3BC54E7D374-low.gif

Equation 17. GUID-7DA08CBA-E151-46A9-8355-7D5C52818DDE-low.gif